upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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641 lines
17 KiB
641 lines
17 KiB
/*
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* ZynqMP clock driver
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*
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* Copyright (C) 2016 Xilinx, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/bitops.h>
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#include <clk-uclass.h>
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#include <clk.h>
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#include <asm/arch/sys_proto.h>
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#include <dm.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const resource_size_t zynqmp_crf_apb_clkc_base = 0xfd1a0020;
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static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
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/* Full power domain clocks */
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#define CRF_APB_APLL_CTRL (zynqmp_crf_apb_clkc_base + 0x00)
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#define CRF_APB_DPLL_CTRL (zynqmp_crf_apb_clkc_base + 0x0c)
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#define CRF_APB_VPLL_CTRL (zynqmp_crf_apb_clkc_base + 0x18)
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#define CRF_APB_PLL_STATUS (zynqmp_crf_apb_clkc_base + 0x24)
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#define CRF_APB_APLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x28)
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#define CRF_APB_DPLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x2c)
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#define CRF_APB_VPLL_TO_LPD_CTRL (zynqmp_crf_apb_clkc_base + 0x30)
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/* Peripheral clocks */
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#define CRF_APB_ACPU_CTRL (zynqmp_crf_apb_clkc_base + 0x40)
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#define CRF_APB_DBG_TRACE_CTRL (zynqmp_crf_apb_clkc_base + 0x44)
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#define CRF_APB_DBG_FPD_CTRL (zynqmp_crf_apb_clkc_base + 0x48)
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#define CRF_APB_DP_VIDEO_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x50)
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#define CRF_APB_DP_AUDIO_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x54)
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#define CRF_APB_DP_STC_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x5c)
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#define CRF_APB_DDR_CTRL (zynqmp_crf_apb_clkc_base + 0x60)
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#define CRF_APB_GPU_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x64)
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#define CRF_APB_SATA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x80)
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#define CRF_APB_PCIE_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x94)
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#define CRF_APB_GDMA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x98)
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#define CRF_APB_DPDMA_REF_CTRL (zynqmp_crf_apb_clkc_base + 0x9c)
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#define CRF_APB_TOPSW_MAIN_CTRL (zynqmp_crf_apb_clkc_base + 0xa0)
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#define CRF_APB_TOPSW_LSBUS_CTRL (zynqmp_crf_apb_clkc_base + 0xa4)
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#define CRF_APB_GTGREF0_REF_CTRL (zynqmp_crf_apb_clkc_base + 0xa8)
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#define CRF_APB_DBG_TSTMP_CTRL (zynqmp_crf_apb_clkc_base + 0xd8)
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/* Low power domain clocks */
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#define CRL_APB_IOPLL_CTRL (zynqmp_crl_apb_clkc_base + 0x00)
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#define CRL_APB_RPLL_CTRL (zynqmp_crl_apb_clkc_base + 0x10)
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#define CRL_APB_PLL_STATUS (zynqmp_crl_apb_clkc_base + 0x20)
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#define CRL_APB_IOPLL_TO_FPD_CTRL (zynqmp_crl_apb_clkc_base + 0x24)
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#define CRL_APB_RPLL_TO_FPD_CTRL (zynqmp_crl_apb_clkc_base + 0x28)
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/* Peripheral clocks */
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#define CRL_APB_USB3_DUAL_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x2c)
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#define CRL_APB_GEM0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x30)
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#define CRL_APB_GEM1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x34)
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#define CRL_APB_GEM2_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x38)
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#define CRL_APB_GEM3_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x3c)
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#define CRL_APB_USB0_BUS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x40)
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#define CRL_APB_USB1_BUS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x44)
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#define CRL_APB_QSPI_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x48)
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#define CRL_APB_SDIO0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x4c)
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#define CRL_APB_SDIO1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x50)
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#define CRL_APB_UART0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x54)
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#define CRL_APB_UART1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x58)
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#define CRL_APB_SPI0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x5c)
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#define CRL_APB_SPI1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x60)
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#define CRL_APB_CAN0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x64)
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#define CRL_APB_CAN1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x68)
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#define CRL_APB_CPU_R5_CTRL (zynqmp_crl_apb_clkc_base + 0x70)
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#define CRL_APB_IOU_SWITCH_CTRL (zynqmp_crl_apb_clkc_base + 0x7c)
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#define CRL_APB_CSU_PLL_CTRL (zynqmp_crl_apb_clkc_base + 0x80)
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#define CRL_APB_PCAP_CTRL (zynqmp_crl_apb_clkc_base + 0x84)
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#define CRL_APB_LPD_SWITCH_CTRL (zynqmp_crl_apb_clkc_base + 0x88)
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#define CRL_APB_LPD_LSBUS_CTRL (zynqmp_crl_apb_clkc_base + 0x8c)
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#define CRL_APB_DBG_LPD_CTRL (zynqmp_crl_apb_clkc_base + 0x90)
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#define CRL_APB_NAND_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x94)
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#define CRL_APB_ADMA_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x98)
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#define CRL_APB_PL0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa0)
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#define CRL_APB_PL1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa4)
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#define CRL_APB_PL2_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xa8)
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#define CRL_APB_PL3_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xac)
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#define CRL_APB_PL0_THR_CNT (zynqmp_crl_apb_clkc_base + 0xb4)
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#define CRL_APB_PL1_THR_CNT (zynqmp_crl_apb_clkc_base + 0xbc)
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#define CRL_APB_PL2_THR_CNT (zynqmp_crl_apb_clkc_base + 0xc4)
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#define CRL_APB_PL3_THR_CNT (zynqmp_crl_apb_clkc_base + 0xdc)
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#define CRL_APB_GEM_TSU_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe0)
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#define CRL_APB_DLL_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe4)
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#define CRL_APB_AMS_REF_CTRL (zynqmp_crl_apb_clkc_base + 0xe8)
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#define CRL_APB_I2C0_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x100)
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#define CRL_APB_I2C1_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x104)
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#define CRL_APB_TIMESTAMP_REF_CTRL (zynqmp_crl_apb_clkc_base + 0x108)
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#define ZYNQ_CLK_MAXDIV 0x3f
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#define CLK_CTRL_DIV1_SHIFT 16
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#define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
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#define CLK_CTRL_DIV0_SHIFT 8
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#define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
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#define CLK_CTRL_SRCSEL_SHIFT 0
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#define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT)
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#define PLLCTRL_FBDIV_MASK 0x7f00
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#define PLLCTRL_FBDIV_SHIFT 8
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#define PLLCTRL_RESET_MASK 1
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#define PLLCTRL_RESET_SHIFT 0
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#define PLLCTRL_BYPASS_MASK 0x8
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#define PLLCTRL_BYPASS_SHFT 3
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#define PLLCTRL_POST_SRC_SHFT 24
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#define PLLCTRL_POST_SRC_MASK (0x7 << PLLCTRL_POST_SRC_SHFT)
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#define NUM_MIO_PINS 77
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enum zynqmp_clk {
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iopll, rpll,
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apll, dpll, vpll,
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iopll_to_fpd, rpll_to_fpd, apll_to_lpd, dpll_to_lpd, vpll_to_lpd,
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acpu, acpu_half,
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dbg_fpd, dbg_lpd, dbg_trace, dbg_tstmp,
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dp_video_ref, dp_audio_ref,
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dp_stc_ref, gdma_ref, dpdma_ref,
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ddr_ref, sata_ref, pcie_ref,
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gpu_ref, gpu_pp0_ref, gpu_pp1_ref,
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topsw_main, topsw_lsbus,
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gtgref0_ref,
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lpd_switch, lpd_lsbus,
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usb0_bus_ref, usb1_bus_ref, usb3_dual_ref, usb0, usb1,
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cpu_r5, cpu_r5_core,
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csu_spb, csu_pll, pcap,
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iou_switch,
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gem_tsu_ref, gem_tsu,
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gem0_ref, gem1_ref, gem2_ref, gem3_ref,
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gem0_rx, gem1_rx, gem2_rx, gem3_rx,
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qspi_ref,
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sdio0_ref, sdio1_ref,
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uart0_ref, uart1_ref,
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spi0_ref, spi1_ref,
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nand_ref,
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i2c0_ref, i2c1_ref, can0_ref, can1_ref, can0, can1,
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dll_ref,
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adma_ref,
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timestamp_ref,
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ams_ref,
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pl0, pl1, pl2, pl3,
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wdt,
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clk_max,
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};
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static const char * const clk_names[clk_max] = {
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"iopll", "rpll", "apll", "dpll",
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"vpll", "iopll_to_fpd", "rpll_to_fpd",
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"apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
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"acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
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"dbg_trace", "dbg_tstmp", "dp_video_ref",
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"dp_audio_ref", "dp_stc_ref", "gdma_ref",
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"dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
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"gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
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"topsw_main", "topsw_lsbus", "gtgref0_ref",
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"lpd_switch", "lpd_lsbus", "usb0_bus_ref",
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"usb1_bus_ref", "usb3_dual_ref", "usb0",
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"usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
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"csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
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"gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
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"gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
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"gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
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"uart0_ref", "uart1_ref", "spi0_ref",
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"spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
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"can0_ref", "can1_ref", "can0", "can1",
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"dll_ref", "adma_ref", "timestamp_ref",
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"ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"
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};
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struct zynqmp_clk_priv {
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unsigned long ps_clk_freq;
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unsigned long video_clk;
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unsigned long pss_alt_ref_clk;
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unsigned long gt_crx_ref_clk;
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unsigned long aux_ref_clk;
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};
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static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
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{
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switch (id) {
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case iopll:
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return CRL_APB_IOPLL_CTRL;
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case rpll:
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return CRL_APB_RPLL_CTRL;
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case apll:
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return CRF_APB_APLL_CTRL;
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case dpll:
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return CRF_APB_DPLL_CTRL;
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case vpll:
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return CRF_APB_VPLL_CTRL;
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case acpu:
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return CRF_APB_ACPU_CTRL;
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case ddr_ref:
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return CRF_APB_DDR_CTRL;
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case qspi_ref:
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return CRL_APB_QSPI_REF_CTRL;
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case gem0_ref:
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return CRL_APB_GEM0_REF_CTRL;
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case gem1_ref:
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return CRL_APB_GEM1_REF_CTRL;
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case gem2_ref:
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return CRL_APB_GEM2_REF_CTRL;
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case gem3_ref:
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return CRL_APB_GEM3_REF_CTRL;
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case uart0_ref:
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return CRL_APB_UART0_REF_CTRL;
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case uart1_ref:
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return CRL_APB_UART1_REF_CTRL;
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case sdio0_ref:
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return CRL_APB_SDIO0_REF_CTRL;
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case sdio1_ref:
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return CRL_APB_SDIO1_REF_CTRL;
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case spi0_ref:
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return CRL_APB_SPI0_REF_CTRL;
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case spi1_ref:
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return CRL_APB_SPI1_REF_CTRL;
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case nand_ref:
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return CRL_APB_NAND_REF_CTRL;
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case i2c0_ref:
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return CRL_APB_I2C0_REF_CTRL;
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case i2c1_ref:
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return CRL_APB_I2C1_REF_CTRL;
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case can0_ref:
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return CRL_APB_CAN0_REF_CTRL;
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case can1_ref:
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return CRL_APB_CAN1_REF_CTRL;
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default:
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debug("Invalid clk id%d\n", id);
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}
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return 0;
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}
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static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl)
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{
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u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
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CLK_CTRL_SRCSEL_SHIFT;
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switch (srcsel) {
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case 2:
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return dpll;
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case 3:
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return vpll;
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case 0 ... 1:
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default:
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return apll;
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}
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}
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static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl)
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{
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u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
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CLK_CTRL_SRCSEL_SHIFT;
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switch (srcsel) {
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case 1:
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return vpll;
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case 0:
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default:
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return dpll;
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}
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}
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static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl)
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{
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u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
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CLK_CTRL_SRCSEL_SHIFT;
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switch (srcsel) {
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case 2:
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return rpll;
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case 3:
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return dpll;
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case 0 ... 1:
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default:
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return iopll;
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}
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}
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static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
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struct zynqmp_clk_priv *priv,
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bool is_pre_src)
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{
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u32 src_sel;
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if (is_pre_src)
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src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
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PLLCTRL_POST_SRC_SHFT;
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else
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src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >>
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PLLCTRL_POST_SRC_SHFT;
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switch (src_sel) {
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case 4:
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return priv->video_clk;
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case 5:
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return priv->pss_alt_ref_clk;
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case 6:
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return priv->aux_ref_clk;
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case 7:
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return priv->gt_crx_ref_clk;
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case 0 ... 3:
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default:
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return priv->ps_clk_freq;
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}
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}
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static ulong zynqmp_clk_get_pll_rate(struct zynqmp_clk_priv *priv,
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enum zynqmp_clk id)
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{
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u32 clk_ctrl, reset, mul;
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ulong freq;
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int ret;
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ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
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if (ret) {
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printf("%s mio read fail\n", __func__);
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return -EIO;
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}
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if (clk_ctrl & PLLCTRL_BYPASS_MASK)
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freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 0);
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else
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freq = zynqmp_clk_get_pll_src(clk_ctrl, priv, 1);
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reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT;
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if (reset && !(clk_ctrl & PLLCTRL_BYPASS_MASK))
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return 0;
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mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
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freq *= mul;
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if (clk_ctrl & (1 << 16))
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freq /= 2;
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return freq;
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}
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static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv,
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enum zynqmp_clk id)
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{
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u32 clk_ctrl, div;
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enum zynqmp_clk pll;
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int ret;
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unsigned long pllrate;
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ret = zynqmp_mmio_read(CRF_APB_ACPU_CTRL, &clk_ctrl);
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if (ret) {
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printf("%s mio read fail\n", __func__);
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return -EIO;
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}
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div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
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pll = zynqmp_clk_get_cpu_pll(clk_ctrl);
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pllrate = zynqmp_clk_get_pll_rate(priv, pll);
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if (IS_ERR_VALUE(pllrate))
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return pllrate;
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return DIV_ROUND_CLOSEST(pllrate, div);
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}
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static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv)
|
|
{
|
|
u32 clk_ctrl, div;
|
|
enum zynqmp_clk pll;
|
|
int ret;
|
|
ulong pllrate;
|
|
|
|
ret = zynqmp_mmio_read(CRF_APB_DDR_CTRL, &clk_ctrl);
|
|
if (ret) {
|
|
printf("%s mio read fail\n", __func__);
|
|
return -EIO;
|
|
}
|
|
|
|
div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
|
|
|
|
pll = zynqmp_clk_get_ddr_pll(clk_ctrl);
|
|
pllrate = zynqmp_clk_get_pll_rate(priv, pll);
|
|
if (IS_ERR_VALUE(pllrate))
|
|
return pllrate;
|
|
|
|
return DIV_ROUND_CLOSEST(pllrate, div);
|
|
}
|
|
|
|
static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
|
|
enum zynqmp_clk id, bool two_divs)
|
|
{
|
|
enum zynqmp_clk pll;
|
|
u32 clk_ctrl, div0;
|
|
u32 div1 = 1;
|
|
int ret;
|
|
ulong pllrate;
|
|
|
|
ret = zynqmp_mmio_read(zynqmp_clk_get_register(id), &clk_ctrl);
|
|
if (ret) {
|
|
printf("%s mio read fail\n", __func__);
|
|
return -EIO;
|
|
}
|
|
|
|
div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
|
|
if (!div0)
|
|
div0 = 1;
|
|
|
|
if (two_divs) {
|
|
div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
|
|
if (!div1)
|
|
div1 = 1;
|
|
}
|
|
|
|
pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
|
|
pllrate = zynqmp_clk_get_pll_rate(priv, pll);
|
|
if (IS_ERR_VALUE(pllrate))
|
|
return pllrate;
|
|
|
|
return
|
|
DIV_ROUND_CLOSEST(
|
|
DIV_ROUND_CLOSEST(pllrate, div0), div1);
|
|
}
|
|
|
|
static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate,
|
|
ulong pll_rate,
|
|
u32 *div0, u32 *div1)
|
|
{
|
|
long new_err, best_err = (long)(~0UL >> 1);
|
|
ulong new_rate, best_rate = 0;
|
|
u32 d0, d1;
|
|
|
|
for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
|
|
for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
|
|
new_rate = DIV_ROUND_CLOSEST(
|
|
DIV_ROUND_CLOSEST(pll_rate, d0), d1);
|
|
new_err = abs(new_rate - rate);
|
|
|
|
if (new_err < best_err) {
|
|
*div0 = d0;
|
|
*div1 = d1;
|
|
best_err = new_err;
|
|
best_rate = new_rate;
|
|
}
|
|
}
|
|
}
|
|
|
|
return best_rate;
|
|
}
|
|
|
|
static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv,
|
|
enum zynqmp_clk id, ulong rate,
|
|
bool two_divs)
|
|
{
|
|
enum zynqmp_clk pll;
|
|
u32 clk_ctrl, div0 = 0, div1 = 0;
|
|
ulong pll_rate, new_rate;
|
|
u32 reg;
|
|
int ret;
|
|
u32 mask;
|
|
|
|
reg = zynqmp_clk_get_register(id);
|
|
ret = zynqmp_mmio_read(reg, &clk_ctrl);
|
|
if (ret) {
|
|
printf("%s mio read fail\n", __func__);
|
|
return -EIO;
|
|
}
|
|
|
|
pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
|
|
pll_rate = zynqmp_clk_get_pll_rate(priv, pll);
|
|
if (IS_ERR_VALUE(pll_rate))
|
|
return pll_rate;
|
|
|
|
clk_ctrl &= ~CLK_CTRL_DIV0_MASK;
|
|
if (two_divs) {
|
|
clk_ctrl &= ~CLK_CTRL_DIV1_MASK;
|
|
new_rate = zynqmp_clk_calc_peripheral_two_divs(rate, pll_rate,
|
|
&div0, &div1);
|
|
clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
|
|
} else {
|
|
div0 = DIV_ROUND_CLOSEST(pll_rate, rate);
|
|
if (div0 > ZYNQ_CLK_MAXDIV)
|
|
div0 = ZYNQ_CLK_MAXDIV;
|
|
new_rate = DIV_ROUND_CLOSEST(rate, div0);
|
|
}
|
|
clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
|
|
|
|
mask = (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT) |
|
|
(ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT);
|
|
|
|
ret = zynqmp_mmio_write(reg, mask, clk_ctrl);
|
|
if (ret) {
|
|
printf("%s mio write fail\n", __func__);
|
|
return -EIO;
|
|
}
|
|
|
|
return new_rate;
|
|
}
|
|
|
|
static ulong zynqmp_clk_get_rate(struct clk *clk)
|
|
{
|
|
struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
|
|
enum zynqmp_clk id = clk->id;
|
|
bool two_divs = false;
|
|
|
|
switch (id) {
|
|
case iopll ... vpll:
|
|
return zynqmp_clk_get_pll_rate(priv, id);
|
|
case acpu:
|
|
return zynqmp_clk_get_cpu_rate(priv, id);
|
|
case ddr_ref:
|
|
return zynqmp_clk_get_ddr_rate(priv);
|
|
case gem0_ref ... gem3_ref:
|
|
case qspi_ref ... can1_ref:
|
|
two_divs = true;
|
|
return zynqmp_clk_get_peripheral_rate(priv, id, two_divs);
|
|
default:
|
|
return -ENXIO;
|
|
}
|
|
}
|
|
|
|
static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
|
|
{
|
|
struct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);
|
|
enum zynqmp_clk id = clk->id;
|
|
bool two_divs = true;
|
|
|
|
switch (id) {
|
|
case gem0_ref ... gem3_ref:
|
|
case qspi_ref ... can1_ref:
|
|
return zynqmp_clk_set_peripheral_rate(priv, id,
|
|
rate, two_divs);
|
|
default:
|
|
return -ENXIO;
|
|
}
|
|
}
|
|
|
|
int soc_clk_dump(void)
|
|
{
|
|
struct udevice *dev;
|
|
int i, ret;
|
|
|
|
ret = uclass_get_device_by_driver(UCLASS_CLK,
|
|
DM_GET_DRIVER(zynqmp_clk), &dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
printf("clk\t\tfrequency\n");
|
|
for (i = 0; i < clk_max; i++) {
|
|
const char *name = clk_names[i];
|
|
if (name) {
|
|
struct clk clk;
|
|
unsigned long rate;
|
|
|
|
clk.id = i;
|
|
ret = clk_request(dev, &clk);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
rate = clk_get_rate(&clk);
|
|
|
|
clk_free(&clk);
|
|
|
|
if ((rate == (unsigned long)-ENOSYS) ||
|
|
(rate == (unsigned long)-ENXIO) ||
|
|
(rate == (unsigned long)-EIO))
|
|
printf("%10s%20s\n", name, "unknown");
|
|
else
|
|
printf("%10s%20lu\n", name, rate);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int zynqmp_get_freq_by_name(char *name, struct udevice *dev, ulong *freq)
|
|
{
|
|
struct clk clk;
|
|
int ret;
|
|
|
|
ret = clk_get_by_name(dev, name, &clk);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to get %s\n", name);
|
|
return ret;
|
|
}
|
|
|
|
*freq = clk_get_rate(&clk);
|
|
if (IS_ERR_VALUE(*freq)) {
|
|
dev_err(dev, "failed to get rate %s\n", name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
static int zynqmp_clk_probe(struct udevice *dev)
|
|
{
|
|
int ret;
|
|
struct zynqmp_clk_priv *priv = dev_get_priv(dev);
|
|
|
|
debug("%s\n", __func__);
|
|
ret = zynqmp_get_freq_by_name("pss_ref_clk", dev, &priv->ps_clk_freq);
|
|
if (ret < 0)
|
|
return -EINVAL;
|
|
|
|
ret = zynqmp_get_freq_by_name("video_clk", dev, &priv->video_clk);
|
|
if (ret < 0)
|
|
return -EINVAL;
|
|
|
|
ret = zynqmp_get_freq_by_name("pss_alt_ref_clk", dev,
|
|
&priv->pss_alt_ref_clk);
|
|
if (ret < 0)
|
|
return -EINVAL;
|
|
|
|
ret = zynqmp_get_freq_by_name("aux_ref_clk", dev, &priv->aux_ref_clk);
|
|
if (ret < 0)
|
|
return -EINVAL;
|
|
|
|
ret = zynqmp_get_freq_by_name("gt_crx_ref_clk", dev,
|
|
&priv->gt_crx_ref_clk);
|
|
if (ret < 0)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct clk_ops zynqmp_clk_ops = {
|
|
.set_rate = zynqmp_clk_set_rate,
|
|
.get_rate = zynqmp_clk_get_rate,
|
|
};
|
|
|
|
static const struct udevice_id zynqmp_clk_ids[] = {
|
|
{ .compatible = "xlnx,zynqmp-clkc" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(zynqmp_clk) = {
|
|
.name = "zynqmp-clk",
|
|
.id = UCLASS_CLK,
|
|
.of_match = zynqmp_clk_ids,
|
|
.probe = zynqmp_clk_probe,
|
|
.ops = &zynqmp_clk_ops,
|
|
.priv_auto_alloc_size = sizeof(struct zynqmp_clk_priv),
|
|
};
|
|
|