upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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205 lines
4.5 KiB
205 lines
4.5 KiB
/*
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* Board specific setup info
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*
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* (C) Copyright 2005-2008 Samsung Electronics
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* Kyungmin Park <kyungmin.park@samsung.com>
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*
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* Derived from board/omap2420h4/platform.S
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/arch/omap2420.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/clocks.h>
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#define APOLLON_CS0_BASE 0x00000000
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#ifdef PRCM_CONFIG_I
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#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907
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#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013
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#define SDRC_RFR_CTRL_0_VAL 0x00044C01
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/* GPMC */
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#define APOLLON_GPMC_CONFIG1_0 0xe30d1201
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#define APOLLON_GPMC_CONFIG2_0 0x000c1000
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#define APOLLON_GPMC_CONFIG3_0 0x00030400
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#define APOLLON_GPMC_CONFIG4_0 0x0B841006
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#define APOLLON_GPMC_CONFIG5_0 0x020F0C11
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#define APOLLON_GPMC_CONFIG6_0 0x00000000
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#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24))
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#elif defined(PRCM_CONFIG_II)
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#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485
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#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C
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#define SDRC_RFR_CTRL_0_VAL 0x00030001
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/* GPMC */
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#define APOLLON_GPMC_CONFIG1_0 0xe30d1201
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#define APOLLON_GPMC_CONFIG2_0 0x00080E81
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#define APOLLON_GPMC_CONFIG3_0 0x00030400
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#define APOLLON_GPMC_CONFIG4_0 0x08041586
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#define APOLLON_GPMC_CONFIG5_0 0x020C090E
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#define APOLLON_GPMC_CONFIG6_0 0x00000000
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#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24))
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#else
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#error "Please configure PRCM schecm"
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#endif
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_TEXT_BASE:
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.word TEXT_BASE /* sdram load addr from config.mk */
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.globl lowlevel_init
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lowlevel_init:
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mov r3, r0 /* save skip information */
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/* Disable watchdog */
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ldr r0, =WD2_BASE
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ldr r1, =WD_UNLOCK1
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str r1, [r0, #WSPR]
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ldr r1, =WD_UNLOCK2
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str r1, [r0, #WSPR]
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#ifdef DEBUG_LED
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/* LED0 OFF */
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ldr r0, =0x480000E5 /* ball AA10, mode 3 */
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mov r1, #0x0b
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strb r1, [r0]
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#endif
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/* Pin muxing for SDRC */
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mov r1, #0x00
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ldr r0, =0x480000A1 /* ball C12, mode 0 */
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strb r1, [r0]
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ldr r0, =0x48000032 /* ball D11, mode 0 */
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strb r1, [r0]
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ldr r0, =0x480000A3 /* ball B13, mode 0 */
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strb r1, [r0]
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/* SDRC setting */
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ldr r0, =OMAP2420_SDRC_BASE
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ldr r1, =0x00000010
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str r1, [r0, #0x10]
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ldr r1, =0x00000100
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str r1, [r0, #0x44]
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/* SDRC CS0 configuration */
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#ifdef CONFIG_APOLLON_PLUS
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ldr r1, =0x01702011
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#else
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ldr r1, =0x00d04011
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#endif
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str r1, [r0, #0x80]
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ldr r1, =SDRC_ACTIM_CTRLA_0_VAL
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str r1, [r0, #0x9C]
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ldr r1, =SDRC_ACTIM_CTRLB_0_VAL
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str r1, [r0, #0xA0]
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ldr r1, =SDRC_RFR_CTRL_0_VAL
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str r1, [r0, #0xA4]
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ldr r1, =0x00000041
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str r1, [r0, #0x70]
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/* Manual command sequence */
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ldr r1, =0x00000007
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str r1, [r0, #0xA8]
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ldr r1, =0x00000000
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str r1, [r0, #0xA8]
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ldr r1, =0x00000001
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str r1, [r0, #0xA8]
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ldr r1, =0x00000002
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str r1, [r0, #0xA8]
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str r1, [r0, #0xA8]
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/*
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* CS0 SDRC Mode register
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* Burst length = 4 - DDR memory
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* Serial mode
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* CAS latency = 3
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*/
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ldr r1, =0x00000032
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str r1, [r0, #0x84]
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/* Note: You MUST set EMR values */
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/* EMR1 & EMR2 */
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ldr r1, =0x00000000
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str r1, [r0, #0x88]
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str r1, [r0, #0x8C]
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#ifdef OLD_SDRC_DLLA_CTRL
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/* SDRC_DLLA_CTRL */
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ldr r1, =0x00007306
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str r1, [r0, #0x60]
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ldr r1, =0x00007303
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str r1, [r0, #0x60]
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#else
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/* SDRC_DLLA_CTRL */
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ldr r1, =0x00000506
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str r1, [r0, #0x60]
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ldr r1, =0x00000503
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str r1, [r0, #0x60]
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#endif
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#ifdef __BROKEN_FEATURE__
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/* SDRC_DLLB_CTRL */
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ldr r1, =0x00000506
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str r1, [r0, #0x68]
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ldr r1, =0x00000503
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str r1, [r0, #0x68]
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#endif
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/* little delay after init */
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mov r2, #0x1800
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1:
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subs r2, r2, #0x1
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bne 1b
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ldr sp, SRAM_STACK
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str ip, [sp] /* stash old link register */
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mov ip, lr /* save link reg across call */
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mov r0, r3 /* pass skip info to s_init */
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bl s_init /* go setup pll,mux,memory */
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ldr ip, [sp] /* restore save ip */
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mov lr, ip /* restore link reg */
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/* back to arch calling code */
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mov pc, lr
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/* the literal pools origin */
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.ltorg
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SRAM_STACK:
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.word LOW_LEVEL_SRAM_STACK
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