upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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416 lines
9.9 KiB
416 lines
9.9 KiB
/*
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* Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
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*
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* Copyright 2007 Embedded Specialties, Inc.
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*
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* Copyright 2004, 2007 Freescale Semiconductor.
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <spd_sdram.h>
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#include <netdev.h>
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#include <tsec.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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DECLARE_GLOBAL_DATA_PTR;
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void local_bus_init(void);
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void sdram_init(void);
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long int fixed_sdram (void);
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int board_early_init_f (void)
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{
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return 0;
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}
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int checkboard (void)
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{
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volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
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volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
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printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
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in_8(rev) >> 4);
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/*
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* Initialize local bus.
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*/
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local_bus_init ();
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out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
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out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
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return 0;
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}
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phys_size_t
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initdram(int board_type)
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{
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long dram_size = 0;
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puts("Initializing\n");
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#if defined(CONFIG_DDR_DLL)
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{
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/*
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* Work around to stabilize DDR DLL MSYNC_IN.
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* Errata DDR9 seems to have been fixed.
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* This is now the workaround for Errata DDR11:
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* Override DLL = 1, Course Adj = 1, Tap Select = 0
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*/
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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out_be32(&gur->ddrdllcr, 0x81000000);
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asm("sync;isync;msync");
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udelay(200);
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}
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#endif
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = fsl_ddr_sdram();
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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#else
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dram_size = fixed_sdram ();
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#endif
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/*
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* SDRAM Initialization
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*/
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sdram_init();
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puts(" DDR: ");
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return dram_size;
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}
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/*
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* Initialize Local Bus
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*/
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void
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local_bus_init(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
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uint clkdiv;
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uint lbc_hz;
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sys_info_t sysinfo;
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get_sys_info(&sysinfo);
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clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
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lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
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out_be32(&gur->lbiuiplldcr1, 0x00078080);
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if (clkdiv == 16) {
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out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
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} else if (clkdiv == 8) {
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out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
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} else if (clkdiv == 4) {
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out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
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}
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setbits_be32(&lbc->lcrr, 0x00030000);
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asm("sync;isync;msync");
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out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
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out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
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}
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/*
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* Initialize SDRAM memory on the Local Bus.
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*/
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void
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sdram_init(void)
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{
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#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
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uint idx;
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volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
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uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
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uint lsdmr_common;
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puts(" SDRAM: ");
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print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
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/*
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* Setup SDRAM Base and Option Registers
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*/
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out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
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asm("msync");
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out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
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asm("msync");
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out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM);
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asm("msync");
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out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM);
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asm("msync");
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out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
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asm("msync");
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out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
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out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
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asm("msync");
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/*
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* MPC8548 uses "new" 15-16 style addressing.
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*/
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lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
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lsdmr_common |= LSDMR_BSMA1516;
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/*
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* Issue PRECHARGE ALL command.
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*/
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out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL);
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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/*
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* Issue 8 AUTO REFRESH commands.
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*/
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for (idx = 0; idx < 8; idx++) {
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out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH);
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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}
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/*
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* Issue 8 MODE-set command.
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*/
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out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW);
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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/*
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* Issue NORMAL OP command.
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*/
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out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL);
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(200); /* Overkill. Must wait > 200 bus cycles */
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#endif /* enable SDRAM init */
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}
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#if defined(CONFIG_SYS_DRAM_TEST)
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int
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testdram(void)
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{
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uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
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uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
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uint *p;
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printf("Testing DRAM from 0x%08x to 0x%08x\n",
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CONFIG_SYS_MEMTEST_START,
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CONFIG_SYS_MEMTEST_END);
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printf("DRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("DRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("DRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("DRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("DRAM test passed.\n");
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return 0;
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}
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#endif
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#if !defined(CONFIG_SPD_EEPROM)
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#define CONFIG_SYS_DDR_CONTROL 0xc300c000
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/*************************************************************************
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* fixed_sdram init -- doesn't use serial presence detect.
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* assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
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************************************************************************/
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long int fixed_sdram (void)
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{
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volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
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out_be32(&ddr->cs0_bnds, 0x0000007f);
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out_be32(&ddr->cs1_bnds, 0x008000ff);
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out_be32(&ddr->cs2_bnds, 0x00000000);
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out_be32(&ddr->cs3_bnds, 0x00000000);
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out_be32(&ddr->cs0_config, 0x80010101);
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out_be32(&ddr->cs1_config, 0x80010101);
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out_be32(&ddr->cs2_config, 0x00000000);
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out_be32(&ddr->cs3_config, 0x00000000);
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out_be32(&ddr->timing_cfg_3, 0x00000000);
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out_be32(&ddr->timing_cfg_0, 0x00220802);
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out_be32(&ddr->timing_cfg_1, 0x38377322);
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out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
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out_be32(&ddr->sdram_cfg, 0x4300C000);
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out_be32(&ddr->sdram_cfg_2, 0x24401000);
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out_be32(&ddr->sdram_mode, 0x23C00542);
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out_be32(&ddr->sdram_mode_2, 0x00000000);
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out_be32(&ddr->sdram_interval, 0x05080100);
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out_be32(&ddr->sdram_md_cntl, 0x00000000);
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out_be32(&ddr->sdram_data_init, 0x00000000);
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out_be32(&ddr->sdram_clk_cntl, 0x03800000);
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asm("sync;isync;msync");
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udelay(500);
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#if defined (CONFIG_DDR_ECC)
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/* Enable ECC checking */
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
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#else
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
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#endif
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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}
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#endif
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#ifdef CONFIG_PCI1
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static struct pci_controller pci1_hose;
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#endif /* CONFIG_PCI1 */
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif /* CONFIG_PCIE1 */
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#ifdef CONFIG_PCI
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void
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pci_init_board(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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struct fsl_pci_info pci_info[2];
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u32 devdisr, pordevsr, porpllsr, io_sel;
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int first_free_busno = 0;
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int num = 0;
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#ifdef CONFIG_PCIE1
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int pcie_configured;
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#endif
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devdisr = in_be32(&gur->devdisr);
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pordevsr = in_be32(&gur->pordevsr);
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porpllsr = in_be32(&gur->porpllsr);
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io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
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#ifdef CONFIG_PCI1
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
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uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
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uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
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uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
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printf (" PCI host: %d bit, %s MHz, %s, %s\n",
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(pci_32) ? 32 : 64,
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(pci_speed == 33000000) ? "33" :
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(pci_speed == 66000000) ? "66" : "unknown",
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pci_clk_sel ? "sync" : "async",
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pci_arb ? "arbiter" : "external-arbiter");
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SET_STD_PCI_INFO(pci_info[num], 1);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pci1_hose, first_free_busno, 0);
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} else {
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printf (" PCI: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
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#endif
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
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#ifdef CONFIG_PCIE1
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pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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SET_STD_PCIE_INFO(pci_info[num], 1);
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printf (" PCIE at base address %lx\n", pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno, 0);
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} else {
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printf (" PCIE: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
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#endif
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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tsec_standard_init(bis);
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pci_eth_init(bis);
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return 0; /* otherwise cpu_eth_init gets run */
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}
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int last_stage_init(void)
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{
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return 0;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI1
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ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
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#endif
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#ifdef CONFIG_PCIE1
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ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
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#endif
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}
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#endif
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