upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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289 lines
8.4 KiB
289 lines
8.4 KiB
/*
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* (C) Copyright 2009
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* Based on board/amcc/canyonlands/canyonlands.c
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* (C) Copyright 2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ppc440.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <i2c.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/4xx_pcie.h>
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#include <asm/gpio.h>
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extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
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DECLARE_GLOBAL_DATA_PTR;
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#define CONFIG_SYS_BCSR3_PCIE 0x10
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int board_early_init_f(void)
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{
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/*
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* Setup the interrupt controller polarities, triggers, etc.
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*/
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic0er, 0x00000000); /* disable all */
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mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
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mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
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mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
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mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic1er, 0x00000000); /* disable all */
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mtdcr(uic1cr, 0x00000000); /* all non-critical */
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mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
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mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
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mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic2sr, 0xffffffff); /* clear all */
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mtdcr(uic2er, 0x00000000); /* disable all */
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mtdcr(uic2cr, 0x00000000); /* all non-critical */
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mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
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mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
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mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(uic2sr, 0xffffffff); /* clear all */
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mtdcr(uic3sr, 0xffffffff); /* clear all */
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mtdcr(uic3er, 0x00000000); /* disable all */
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mtdcr(uic3cr, 0x00000000); /* all non-critical */
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mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
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mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
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mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(uic3sr, 0xffffffff); /* clear all */
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/*
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* Configure PFC (Pin Function Control) registers
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* enable GPIO 49-63
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* UART0: 4 pins
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*/
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mtsdr(SDR0_PFC0, 0x00007fff);
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mtsdr(SDR0_PFC1, 0x00040000);
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/* Enable PCI host functionality in SDR0_PCI0 */
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mtsdr(SDR0_PCI0, 0xe0000000);
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mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
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/* Setup PLB4-AHB bridge based on the system address map */
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mtdcr(AHB_TOP, 0x8000004B);
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mtdcr(AHB_BOT, 0x8000004B);
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/*
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* Configure USB-STP pins as alternate and not GPIO
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* It seems to be neccessary to configure the STP pins as GPIO
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* input at powerup (perhaps while USB reset is asserted). So
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* we configure those pins to their "real" function now.
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*/
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gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
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gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
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/* Trigger board component reset */
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out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
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out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
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udelay(50);
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out_le16((void *)CONFIG_SYS_IO_BASE, 0xffbf);
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out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffbf);
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udelay(50);
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out_le16((void *)CONFIG_SYS_IO_BASE, 0xffff);
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out_le16((void *)CONFIG_SYS_IO_BASE + 0x100, 0xffff);
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return 0;
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}
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int get_cpu_num(void)
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{
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int cpu = NA_OR_UNKNOWN_CPU;
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return cpu;
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}
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int checkboard(void)
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{
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char *s = getenv("serial#");
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#ifdef CONFIG_DEVCONCENTER
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printf("Board: DevCon-Center");
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#else
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printf("Board: CompactCenter");
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#endif
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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return 0;
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}
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/*
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* pci_target_init
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*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*/
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#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
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void pci_target_init(struct pci_controller *hose)
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{
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/*
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* Disable everything
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*/
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out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
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out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
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out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
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out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
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/*
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* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
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* strapping options to not support sizes such as 128/256 MB.
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*/
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out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
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out_le32((void *)PCIX0_PIM0LAH, 0);
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out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
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out_le32((void *)PCIX0_BAR0, 0);
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/*
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* Program the board's subsystem id/vendor id
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*/
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out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
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out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
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out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
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}
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#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
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#if defined(CONFIG_PCI)
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/*
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* is_pci_host
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*/
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int is_pci_host(struct pci_controller *hose)
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{
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/* Board is always configured as host. */
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return 1;
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}
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#endif /* CONFIG_PCI */
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int board_early_init_r(void)
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{
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/*
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* CompactCenter has 64MBytes, DevCon-Center 128MBytes of NOR FLASH
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* (Spansion 29GL512), but the boot EBC mapping only supports a maximum
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* of 16MBytes (4.ff00.0000 - 4.ffff.ffff).
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* To solve this problem, the FLASH has to get remapped to another
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* EBC address which accepts bigger regions:
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*
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* 0xfn00.0000 -> 4.cn00.0000
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*/
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u32 bxcr_bw = (CONFIG_SYS_FLASH_SIZE == 128 << 20) ?
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EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB;
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/* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */
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mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L
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| bxcr_bw
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| EBC_BXCR_BU_RW
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| EBC_BXCR_BW_16BIT);
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/* Remove TLB entry of boot EBC mapping */
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remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
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/* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
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program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
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CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
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/*
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* Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
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* 0xfc00.0000 is possible
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*/
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/*
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* Clear potential errors resulting from auto-calibration.
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* If not done, then we could get an interrupt later on when
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* exceptions are enabled.
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*/
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set_mcsr(get_mcsr());
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return 0;
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}
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int misc_init_r(void)
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{
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u32 sdr0_srst1 = 0;
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u32 eth_cfg;
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/*
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* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
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* This is board specific, so let's do it here.
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*/
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mfsdr(SDR0_ETH_CFG, eth_cfg);
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/* disable SGMII mode */
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eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
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SDR0_ETH_CFG_SGMII1_ENABLE |
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SDR0_ETH_CFG_SGMII0_ENABLE);
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/* Set the for 2 RGMII mode */
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/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
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eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
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eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
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mtsdr(SDR0_ETH_CFG, eth_cfg);
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/*
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* The AHB Bridge core is held in reset after power-on or reset
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* so enable it now
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*/
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mfsdr(SDR0_SRST1, sdr0_srst1);
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sdr0_srst1 &= ~SDR0_SRST1_AHB;
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mtsdr(SDR0_SRST1, sdr0_srst1);
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return 0;
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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extern void __ft_board_setup(void *blob, bd_t *bd);
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void ft_board_setup(void *blob, bd_t *bd)
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{
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__ft_board_setup(blob, bd);
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fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
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"disabled", sizeof("disabled"), 1);
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fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
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"disabled", sizeof("disabled"), 1);
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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