upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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245 lines
9.2 KiB
245 lines
9.2 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Faraday FTSDC010 Secure Digital Memory Card Host Controller
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*
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* Copyright (C) 2011 Andes Technology Corporation
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*/
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#ifndef __FTSDC010_H
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#define __FTSDC010_H
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#ifndef __ASSEMBLY__
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/* sd controller register */
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struct ftsdc010_mmc {
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unsigned int cmd; /* 0x00 - command reg */
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unsigned int argu; /* 0x04 - argument reg */
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unsigned int rsp0; /* 0x08 - response reg0 */
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unsigned int rsp1; /* 0x0c - response reg1 */
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unsigned int rsp2; /* 0x10 - response reg2 */
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unsigned int rsp3; /* 0x14 - response reg3 */
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unsigned int rsp_cmd; /* 0x18 - responded cmd reg */
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unsigned int dcr; /* 0x1c - data control reg */
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unsigned int dtr; /* 0x20 - data timer reg */
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unsigned int dlr; /* 0x24 - data length reg */
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unsigned int status; /* 0x28 - status reg */
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unsigned int clr; /* 0x2c - clear reg */
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unsigned int int_mask; /* 0x30 - intrrupt mask reg */
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unsigned int pcr; /* 0x34 - power control reg */
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unsigned int ccr; /* 0x38 - clock contorl reg */
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unsigned int bwr; /* 0x3c - bus width reg */
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unsigned int dwr; /* 0x40 - data window reg */
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#ifndef CONFIG_FTSDC010_SDIO
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unsigned int feature; /* 0x44 - feature reg */
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unsigned int rev; /* 0x48 - revision reg */
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#else
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unsigned int mmc_intr_time; /* 0x44 - MMC int resp time reg */
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unsigned int gpo; /* 0x48 - gerenal purpose output */
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unsigned int reserved[8]; /* 0x50 - 0x68 reserved */
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unsigned int sdio_ctrl1; /* 0x6c - SDIO control reg 1 */
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unsigned int sdio_ctrl2; /* 0x70 - SDIO control reg 2 */
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unsigned int sdio_status; /* 0x74 - SDIO status regi */
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unsigned int reserved1[9]; /* 0x78 - 0x98 reserved */
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unsigned int feature; /* 0x9c - feature reg */
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unsigned int rev; /* 0xa0 - revision reg */
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#endif /* CONFIG_FTSDC010_SDIO */
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};
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struct mmc_host {
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struct ftsdc010_mmc *reg;
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unsigned int version; /* SDHCI spec. version */
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unsigned int clock; /* Current clock (MHz) */
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unsigned int fifo_len; /* bytes */
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unsigned int last_opcode; /* Last OP Code */
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unsigned int card_type; /* Card type */
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};
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/* functions */
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int ftsdc010_mmc_init(int dev_index);
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#endif /* __ASSEMBLY__ */
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/* global defines */
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#define FTSDC010_CMD_RETRY 0x100000
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#define FTSDC010_PIO_RETRY 100 /* pio retry times */
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#define FTSDC010_DELAY_UNIT 100 /* 100 us */
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/* define from Linux kernel - include/linux/mmc/card.h */
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#define MMC_TYPE_SDIO 2 /* SDIO card */
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/* define for mmc layer */
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#define MMC_DATA_BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
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/* this part is strange */
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#define FTSDC010_SDIO_CTRL1_REG 0x0000006C
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#define FTSDC010_SDIO_CTRL2_REG 0x0000006C
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#define FTSDC010_SDIO_STATUS_REG 0x00000070
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/* 0x00 - command register */
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#define FTSDC010_CMD_IDX(x) (((x) & 0x3f) << 0)
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#define FTSDC010_CMD_NEED_RSP (1 << 6)
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#define FTSDC010_CMD_LONG_RSP (1 << 7)
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#define FTSDC010_CMD_APP_CMD (1 << 8)
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#define FTSDC010_CMD_CMD_EN (1 << 9)
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#define FTSDC010_CMD_SDC_RST (1 << 10)
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#define FTSDC010_CMD_MMC_INT_STOP (1 << 11)
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/* 0x18 - responded command register */
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#define FTSDC010_RSP_CMD_IDX(x) (((x) >> 0) & 0x3f)
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#define FTSDC010_RSP_CMD_APP (1 << 6)
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/* 0x1c - data control register */
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#define FTSDC010_DCR_BLK_SIZE(x) (((x) & 0xf) << 0)
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#define FTSDC010_DCR_DATA_WRITE (1 << 4)
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#define FTSDC010_DCR_DMA_EN (1 << 5)
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#define FTSDC010_DCR_DATA_EN (1 << 6)
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#ifdef CONFIG_FTSDC010_SDIO
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#define FTSDC010_DCR_FIFOTH (1 << 7)
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#define FTSDC010_DCR_DMA_TYPE(x) (((x) & 0x3) << 8)
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#define FTSDC010_DCR_FIFO_RST (1 << 10)
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#endif /* CONFIG_FTSDC010_SDIO */
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#define FTSDC010_DCR_DMA_TYPE_1 0x0 /* Single r/w */
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#define FTSDC010_DCR_DMA_TYPE_4 0x1 /* Burst 4 r/w */
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#define FTSDC010_DCR_DMA_TYPE_8 0x2 /* Burst 8 r/w */
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#define FTSDC010_DCR_BLK_BYTES(x) (ffs(x) - 1) /* 1B - 2048B */
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/* CPRM related define */
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#define FTSDC010_CPRM_DATA_CHANGE_ENDIAN_EN 0x000008
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#define FTSDC010_CPRM_DATA_SWAP_HL_EN 0x000010
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/* 0x28 - status register */
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#define FTSDC010_STATUS_RSP_CRC_FAIL (1 << 0)
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#define FTSDC010_STATUS_DATA_CRC_FAIL (1 << 1)
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#define FTSDC010_STATUS_RSP_TIMEOUT (1 << 2)
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#define FTSDC010_STATUS_DATA_TIMEOUT (1 << 3)
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#define FTSDC010_STATUS_RSP_CRC_OK (1 << 4)
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#define FTSDC010_STATUS_DATA_CRC_OK (1 << 5)
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#define FTSDC010_STATUS_CMD_SEND (1 << 6)
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#define FTSDC010_STATUS_DATA_END (1 << 7)
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#define FTSDC010_STATUS_FIFO_URUN (1 << 8)
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#define FTSDC010_STATUS_FIFO_ORUN (1 << 9)
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#define FTSDC010_STATUS_CARD_CHANGE (1 << 10)
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#define FTSDC010_STATUS_CARD_DETECT (1 << 11)
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#define FTSDC010_STATUS_WRITE_PROT (1 << 12)
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#ifdef CONFIG_FTSDC010_SDIO
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#define FTSDC010_STATUS_CP_READY (1 << 13) /* reserved ? */
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#define FTSDC010_STATUS_CP_BUF_READY (1 << 14) /* reserved ? */
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#define FTSDC010_STATUS_PLAIN_TEXT_READY (1 << 15) /* reserved ? */
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#define FTSDC010_STATUS_SDIO_IRPT (1 << 16) /* SDIO card intr */
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#define FTSDC010_STATUS_DATA0_STATUS (1 << 17)
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#endif /* CONFIG_FTSDC010_SDIO */
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#define FTSDC010_STATUS_RSP_ERROR \
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(FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_RSP_TIMEOUT)
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#define FTSDC010_STATUS_RSP_MASK \
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(FTSDC010_STATUS_RSP_ERROR | FTSDC010_STATUS_RSP_CRC_OK)
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#define FTSDC010_STATUS_DATA_ERROR \
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(FTSDC010_STATUS_DATA_CRC_FAIL | FTSDC010_STATUS_DATA_TIMEOUT)
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#define FTSDC010_STATUS_DATA_MASK \
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(FTSDC010_STATUS_DATA_ERROR | FTSDC010_STATUS_DATA_CRC_OK \
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| FTSDC010_STATUS_DATA_END)
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/* 0x2c - clear register */
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#define FTSDC010_CLR_RSP_CRC_FAIL (1 << 0)
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#define FTSDC010_CLR_DATA_CRC_FAIL (1 << 1)
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#define FTSDC010_CLR_RSP_TIMEOUT (1 << 2)
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#define FTSDC010_CLR_DATA_TIMEOUT (1 << 3)
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#define FTSDC010_CLR_RSP_CRC_OK (1 << 4)
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#define FTSDC010_CLR_DATA_CRC_OK (1 << 5)
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#define FTSDC010_CLR_CMD_SEND (1 << 6)
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#define FTSDC010_CLR_DATA_END (1 << 7)
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#define FTSDC010_STATUS_FIFO_URUN (1 << 8) /* reserved ? */
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#define FTSDC010_STATUS_FIFO_ORUN (1 << 9) /* reserved ? */
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#define FTSDC010_CLR_CARD_CHANGE (1 << 10)
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#ifdef CONFIG_FTSDC010_SDIO
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#define FTSDC010_CLR_SDIO_IRPT (1 << 16)
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#endif /* CONFIG_FTSDC010_SDIO */
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/* 0x30 - interrupt mask register */
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#define FTSDC010_INT_MASK_RSP_CRC_FAIL (1 << 0)
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#define FTSDC010_INT_MASK_DATA_CRC_FAIL (1 << 1)
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#define FTSDC010_INT_MASK_RSP_TIMEOUT (1 << 2)
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#define FTSDC010_INT_MASK_DATA_TIMEOUT (1 << 3)
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#define FTSDC010_INT_MASK_RSP_CRC_OK (1 << 4)
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#define FTSDC010_INT_MASK_DATA_CRC_OK (1 << 5)
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#define FTSDC010_INT_MASK_CMD_SEND (1 << 6)
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#define FTSDC010_INT_MASK_DATA_END (1 << 7)
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#define FTSDC010_INT_MASK_FIFO_URUN (1 << 8)
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#define FTSDC010_INT_MASK_FIFO_ORUN (1 << 9)
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#define FTSDC010_INT_MASK_CARD_CHANGE (1 << 10)
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#ifdef CONFIG_FTSDC010_SDIO
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#define FTSDC010_INT_MASK_CP_READY (1 << 13)
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#define FTSDC010_INT_MASK_CP_BUF_READY (1 << 14)
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#define FTSDC010_INT_MASK_PLAIN_TEXT_READY (1 << 15)
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#define FTSDC010_INT_MASK_SDIO_IRPT (1 << 16)
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#define FTSDC010_STATUS_DATA0_STATUS (1 << 17)
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#endif /* CONFIG_FTSDC010_SDIO */
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/* ? */
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#define FTSDC010_CARD_INSERT 0x0
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#define FTSDC010_CARD_REMOVE FTSDC010_STATUS_REG_CARD_DETECT
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/* 0x34 - power control register */
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#define FTSDC010_PCR_POWER(x) (((x) & 0xf) << 0)
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#define FTSDC010_PCR_POWER_ON (1 << 4)
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/* 0x38 - clock control register */
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#define FTSDC010_CCR_CLK_DIV(x) (((x) & 0x7f) << 0)
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#define FTSDC010_CCR_CLK_SD (1 << 7) /* 0: MMC, 1: SD */
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#define FTSDC010_CCR_CLK_DIS (1 << 8)
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#define FTSDC010_CCR_CLK_HISPD (1 << 9) /* high speed */
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/* card type */
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#define FTSDC010_CARD_TYPE_SD FTSDC010_CLOCK_REG_CARD_TYPE
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#define FTSDC010_CARD_TYPE_MMC 0x0
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/* 0x3c - bus width register */
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#define FTSDC010_BWR_MODE_1BIT (1 << 0) /* 1 bit mode enabled */
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#define FTSDC010_BWR_MODE_8BIT (1 << 1) /* 8 bit mode enabled */
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#define FTSDC010_BWR_MODE_4BIT (1 << 2) /* 4 bit mode enabled */
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#define FTSDC010_BWR_MODE_MASK (7 << 0)
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#define FTSDC010_BWR_MODE_SHIFT (0)
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#define FTSDC010_BWR_CAPS_1BIT (0 << 3) /* 1 bits mode supported */
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#define FTSDC010_BWR_CAPS_4BIT (1 << 3) /* 1,4 bits mode supported */
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#define FTSDC010_BWR_CAPS_8BIT (2 << 3) /* 1,4,8 bits mode supported */
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#define FTSDC010_BWR_CAPS_MASK (3 << 3)
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#define FTSDC010_BWR_CAPS_SHIFT (3)
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#define FTSDC010_BWR_CARD_DETECT (1 << 5)
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/* 0x44 or 0x9c - feature register */
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#define FTSDC010_FEATURE_FIFO_DEPTH(x) (((x) >> 0) & 0xff)
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#define FTSDC010_FEATURE_CPRM_FUNCTION (1 << 8)
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#define FTSDC010_FIFO_DEPTH_4 0x04
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#define FTSDC010_FIFO_DEPTH_8 0x08
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#define FTSDC010_FIFO_DEPTH_16 0x10
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/* 0x48 or 0xa0 - revision register */
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#define FTSDC010_REV_REVISION(x) (((x) & 0xff) >> 0)
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#define FTSDC010_REV_MINOR(x) (((x) & 0xff00) >> 8)
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#define FTSDC010_REV_MAJOR(x) (((x) & 0xffff0000) >> 16)
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#ifdef CONFIG_FTSDC010_SDIO
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/* 0x44 - general purpose output */
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#define FTSDC010_GPO_PORT(x) (((x) & 0xf) << 0)
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/* 0x6c - sdio control register 1 */
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#define FTSDC010_SDIO_CTRL1_SDIO_BLK_SIZE(x) (((x) & 0xfff) << 0)
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#define FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE (1 << 12)
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#define FTSDC010_SDIO_CTRL1_READ_WAIT_EN (1 << 13)
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#define FTSDC010_SDIO_CTRL1_SDIO_ENABLE (1 << 14)
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#define FTSDC010_SDIO_CTRL1_SDIO_BLK_NO(x) (((x) & 0x1ff) << 15)
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/* 0x70 - sdio control register 2 */
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#define FTSDC010_SDIO_CTRL2_SUSP_READ_WAIT (1 << 0)
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#define FTSDC010_SDIO_CTRL2_SUSP_CMD_ABORT (1 << 1)
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/* 0x74 - sdio status register */
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#define FTSDC010_SDIO_STATUS_SDIO_BLK_CNT(x) (((x) >> 0) & 0x1ffff)
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#define FTSDC010_SDIO_STATUS_FIFO_REMAIN_NO(x) (((x) >> 17) & 0xef)
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#endif /* CONFIG_FTSDC010_SDIO */
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#endif /* __FTSDC010_H */
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