upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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358 lines
11 KiB
358 lines
11 KiB
/*
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* Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <spd_sdram.h>
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#include <i2c.h>
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#define BOOT_SMALL_FLASH 32 /* 00100000 */
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#define FLASH_ONBD_N 2 /* 00000010 */
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#define FLASH_SRAM_SEL 1 /* 00000001 */
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long int fixed_sdram (void);
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int board_pre_init (void)
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{
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unsigned long sdrreg;
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/* TBS: Setup the GPIO access for the user LEDs */
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mfsdr(sdr_pfc0, sdrreg);
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mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00);
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out32(CFG_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
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LED0_OFF();
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LED1_OFF();
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LED2_OFF();
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LED3_OFF();
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/*--------------------------------------------------------------------
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* Setup the external bus controller/chip selects
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*-------------------------------------------------------------------*/
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/* set the bus controller */
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mtebc (pb0ap, 0x04055200); /* FLASH/SRAM */
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mtebc (pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr (uic0sr, 0xffffffff); /* clear all */
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mtdcr (uic0er, 0x00000000); /* disable all */
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mtdcr (uic0cr, 0x00000003); /* SMI & UIC1 crit are critical */
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mtdcr (uic0pr, 0xfffffe00); /* per ref-board manual */
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mtdcr (uic0tr, 0x01c00000); /* per ref-board manual */
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mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic0sr, 0xffffffff); /* clear all */
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mtdcr (uic1sr, 0xffffffff); /* clear all */
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mtdcr (uic1er, 0x00000000); /* disable all */
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mtdcr (uic1cr, 0x00000000); /* all non-critical */
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mtdcr (uic1pr, 0xffffc0ff); /* per ref-board manual */
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mtdcr (uic1tr, 0x00ff8000); /* per ref-board manual */
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mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic1sr, 0xffffffff); /* clear all */
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mtdcr (uic2sr, 0xffffffff); /* clear all */
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mtdcr (uic2er, 0x00000000); /* disable all */
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mtdcr (uic2cr, 0x00000000); /* all non-critical */
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mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
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mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
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mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic2sr, 0xffffffff); /* clear all */
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mtdcr (uicb0sr, 0xfc000000); /* clear all */
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mtdcr (uicb0er, 0x00000000); /* disable all */
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mtdcr (uicb0cr, 0x00000000); /* all non-critical */
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mtdcr (uicb0pr, 0xfc000000); /* */
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mtdcr (uicb0tr, 0x00000000); /* */
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mtdcr (uicb0vr, 0x00000001); /* */
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LED0_ON();
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return 0;
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}
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int checkboard (void)
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{
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sys_info_t sysinfo;
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get_sys_info (&sysinfo);
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printf ("Board: XES XPedite1000 440GX\n");
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printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
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printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
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printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
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printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
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printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
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return (0);
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}
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long int initdram (int board_type)
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{
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long dram_size = 0;
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = spd_sdram (0);
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#else
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dram_size = fixed_sdram ();
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#endif
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return dram_size;
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}
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#if defined(CFG_DRAM_TEST)
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int testdram (void)
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{
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uint *pstart = (uint *) 0x00000000;
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uint *pend = (uint *) 0x08000000;
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uint *p;
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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return 0;
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}
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#endif
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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*
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* Assumes: 128 MB, non-ECC, non-registered
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* PLB @ 133 MHz
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*
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************************************************************************/
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long int fixed_sdram (void)
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{
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uint reg;
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/*--------------------------------------------------------------------
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* Setup some default
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*------------------------------------------------------------------*/
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mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
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mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
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mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
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mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
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mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
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/*--------------------------------------------------------------------
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* Setup for board-specific specific mem
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*------------------------------------------------------------------*/
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/*
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* Following for CAS Latency = 2.5 @ 133 MHz PLB
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*/
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mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
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mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
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/* RA=10 RD=3 */
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mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
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mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
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mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
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udelay (400); /* Delay 200 usecs (min) */
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/*--------------------------------------------------------------------
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* Enable the controller, then wait for DCEN to complete
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*------------------------------------------------------------------*/
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mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
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for (;;) {
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mfsdram (mem_mcsts, reg);
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if (reg & 0x80000000)
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break;
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}
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return (128 * 1024 * 1024); /* 128 MB */
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}
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#endif /* !defined(CONFIG_SPD_EEPROM) */
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/*************************************************************************
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* pci_pre_init
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*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
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int pci_pre_init(struct pci_controller * hose )
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{
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unsigned long strap;
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/*--------------------------------------------------------------------------+
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* TBS:
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* The xpedite1k is a PrPMC board, however for our purposes it is the host
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*--------------------------------------------------------------------------*/
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strap = mfdcr(cpc0_strp1);
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if( (strap & 0x00100000) == 0 ){
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printf("PCI: CPC0_STRP1[PAE] not set.\n");
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return 0;
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}
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return 1;
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
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/*************************************************************************
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* pci_target_init
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*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
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void pci_target_init(struct pci_controller * hose )
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{
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DECLARE_GLOBAL_DATA_PTR;
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/*--------------------------------------------------------------------------+
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* Disable everything
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*--------------------------------------------------------------------------*/
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out32r( PCIX0_PIM0SA, 0 ); /* disable */
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out32r( PCIX0_PIM1SA, 0 ); /* disable */
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out32r( PCIX0_PIM2SA, 0 ); /* disable */
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out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
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/*--------------------------------------------------------------------------+
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* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
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* options to not support sizes such as 128/256 MB.
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*--------------------------------------------------------------------------*/
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out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
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out32r( PCIX0_PIM0LAH, 0 );
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out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
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out32r( PCIX0_BAR0, 0 );
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/*--------------------------------------------------------------------------+
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* Program the board's subsystem id/vendor id
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*--------------------------------------------------------------------------*/
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out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
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out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
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out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
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/*************************************************************************
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* is_pci_host
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*
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*
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************************************************************************/
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#if defined(CONFIG_PCI)
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int is_pci_host(struct pci_controller *hose)
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{
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/* The ebony board is always configured as host. */
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/* TBS: The xpedite1k is not necessarily the host, however for our purposes, it is. */
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return(1);
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}
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#endif /* defined(CONFIG_PCI) */
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#ifdef CONFIG_POST
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/*
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* Returns 1 if keys pressed to start the power-on long-running tests
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* Called from board_init_f().
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*/
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int post_hotkeys_pressed(void)
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{
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return (ctrlc());
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}
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void post_word_store (ulong a)
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{
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volatile ulong *save_addr =
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(volatile ulong *)(CFG_POST_WORD_ADDR);
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*save_addr = a;
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}
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ulong post_word_load (void)
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{
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volatile ulong *save_addr =
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(volatile ulong *)(CFG_POST_WORD_ADDR);
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return *save_addr;
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}
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#endif
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/*-----------------------------------------------------------------------------
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* board_get_enetaddr -- Read the MAC Addresses in the I2C EEPROM
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*-----------------------------------------------------------------------------
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*/
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static int enetaddr_num = 0;
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void board_get_enetaddr (uchar * enet)
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{
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int i;
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unsigned char buff[0x100], *cp;
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/* Initialize I2C */
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i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
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/* Read 256 bytes in EEPROM */
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i2c_read (0x50, 0, 1, buff, 0x100);
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if (enetaddr_num == 0) {
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cp = &buff[0xF4];
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enetaddr_num = 1;
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}
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else
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cp = &buff[0xFA];
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for (i = 0; i < 6; i++,cp++)
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enet[i] = *cp;
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printf ("MAC address = %02x:%02x:%02x:%02x:%02x:%02x\n",
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enet[0], enet[1], enet[2], enet[3], enet[4], enet[5]);
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}
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