upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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182 lines
4.1 KiB
182 lines
4.1 KiB
/*
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* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <clk.h>
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#include <dm/device.h>
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#include "clk-uniphier.h"
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#define UNIPHIER_MIO_CLK_GATE_SD(ch, idx) \
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{ \
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.index = (idx), \
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.reg = 0x20 + 0x200 * (ch), \
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.mask = 0x00000100, \
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.data = 0x00000100, \
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}, \
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{ \
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.index = (idx), \
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.reg = 0x110 + 0x200 * (ch), \
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.mask = 0x00000001, \
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.data = 0x00000001, \
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}
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#define UNIPHIER_MIO_CLK_RATE_SD(ch, idx) \
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{ \
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.index = (idx), \
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.reg = 0x30 + 0x200 * (ch), \
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.mask = 0x00031300, \
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.data = 0x00000000, \
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.rate = 44444444, \
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}, \
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{ \
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.index = (idx), \
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.reg = 0x30 + 0x200 * (ch), \
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.mask = 0x00031300, \
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.data = 0x00010000, \
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.rate = 33333333, \
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}, \
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{ \
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.index = (idx), \
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.reg = 0x30 + 0x200 * (ch), \
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.mask = 0x00031300, \
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.data = 0x00020000, \
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.rate = 50000000, \
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}, \
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{ \
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.index = (idx), \
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.reg = 0x30 + 0x200 * (ch), \
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.mask = 0x00031300, \
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.data = 0x00020000, \
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.rate = 66666666, \
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}, \
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{ \
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.index = (idx), \
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.reg = 0x30 + 0x200 * (ch), \
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.mask = 0x00031300, \
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.data = 0x00001000, \
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.rate = 100000000, \
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}, \
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{ \
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.index = (idx), \
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.reg = 0x30 + 0x200 * (ch), \
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.mask = 0x00031300, \
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.data = 0x00001100, \
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.rate = 40000000, \
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}, \
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{ \
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.index = (idx), \
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.reg = 0x30 + 0x200 * (ch), \
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.mask = 0x00031300, \
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.data = 0x00001200, \
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.rate = 25000000, \
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}, \
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{ \
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.index = (idx), \
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.reg = 0x30 + 0x200 * (ch), \
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.mask = 0x00031300, \
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.data = 0x00001300, \
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.rate = 22222222, \
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}
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#define UNIPHIER_MIO_CLK_GATE_USB(ch, idx) \
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{ \
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.index = (idx), \
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.reg = 0x20 + 0x200 * (ch), \
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.mask = 0x30000000, \
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.data = 0x30000000, \
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}, \
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{ \
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.index = (idx), \
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.reg = 0x110 + 0x200 * (ch), \
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.mask = 0x01000000, \
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.data = 0x01000000, \
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}, \
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{ \
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.index = (idx), \
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.reg = 0x114 + 0x200 * (ch), \
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.mask = 0x00000001, \
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.data = 0x00000001, \
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}
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#define UNIPHIER_MIO_CLK_GATE_DMAC(idx) \
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{ \
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.index = (idx), \
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.reg = 0x20, \
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.mask = 0x02000000, \
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.data = 0x02000000, \
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}, \
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{ \
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.index = (idx), \
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.reg = 0x110, \
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.mask = 0x00020000, \
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.data = 0x00020000, \
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}
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static struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = {
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UNIPHIER_MIO_CLK_GATE_SD(0, 0),
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UNIPHIER_MIO_CLK_GATE_SD(1, 1),
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UNIPHIER_MIO_CLK_GATE_SD(2, 2), /* for PH1-Pro4 only */
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UNIPHIER_MIO_CLK_GATE_USB(0, 3),
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UNIPHIER_MIO_CLK_GATE_USB(1, 4),
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UNIPHIER_MIO_CLK_GATE_USB(2, 5),
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UNIPHIER_MIO_CLK_GATE_DMAC(6),
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UNIPHIER_MIO_CLK_GATE_USB(3, 7), /* for PH1-sLD3 only */
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};
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static struct uniphier_clk_rate_data uniphier_mio_clk_rate[] = {
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UNIPHIER_MIO_CLK_RATE_SD(0, 0),
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UNIPHIER_MIO_CLK_RATE_SD(1, 1),
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UNIPHIER_MIO_CLK_RATE_SD(2, 2), /* for PH1-Pro4 only */
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};
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static struct uniphier_clk_soc_data uniphier_mio_clk_data = {
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.gate = uniphier_mio_clk_gate,
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.nr_gate = ARRAY_SIZE(uniphier_mio_clk_gate),
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.rate = uniphier_mio_clk_rate,
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.nr_rate = ARRAY_SIZE(uniphier_mio_clk_rate),
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};
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static const struct udevice_id uniphier_mio_clk_match[] = {
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{
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.compatible = "socionext,ph1-sld3-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,ph1-ld4-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,ph1-pro4-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,ph1-sld8-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,ph1-pro5-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,proxstream2-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{
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.compatible = "socionext,ph1-ld20-mioctrl",
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.data = (ulong)&uniphier_mio_clk_data,
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},
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(uniphier_mio_clk) = {
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.name = "uniphier-mio-clk",
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.id = UCLASS_CLK,
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.of_match = uniphier_mio_clk_match,
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.probe = uniphier_clk_probe,
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.remove = uniphier_clk_remove,
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.priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
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.ops = &uniphier_clk_ops,
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};
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