upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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331 lines
8.0 KiB
331 lines
8.0 KiB
/*
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* Cache-handling routined for MIPS CPUs
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*
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/cacheops.h>
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#define RA t8
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/*
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* 16kB is the maximum size of instruction and data caches on MIPS 4K,
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* 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
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*
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* Note that the above size is the maximum size of primary cache. U-Boot
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* doesn't have L2 cache support for now.
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*/
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#define MIPS_MAX_CACHE_SIZE 0x10000
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#define INDEX_BASE CKSEG0
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.macro cache_op op addr
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.set push
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.set noreorder
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.set mips3
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cache \op, 0(\addr)
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.set pop
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.endm
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/*
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* cacheop macro to automate cache operations
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* first some helpers...
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*/
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#define _mincache(size, maxsize) \
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bltu size,maxsize,9f ; \
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move size,maxsize ; \
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9:
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#define _align(minaddr, maxaddr, linesize) \
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.set noat ; \
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subu AT,linesize,1 ; \
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not AT ; \
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and minaddr,AT ; \
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addu maxaddr,-1 ; \
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and maxaddr,AT ; \
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.set at
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/* general operations */
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#define doop1(op1) \
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cache op1,0(a0)
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#define doop2(op1, op2) \
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cache op1,0(a0) ; \
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nop ; \
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cache op2,0(a0)
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/* specials for cache initialisation */
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#define doop1lw(op1) \
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lw zero,0(a0)
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#define doop1lw1(op1) \
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cache op1,0(a0) ; \
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lw zero,0(a0) ; \
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cache op1,0(a0)
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#define doop121(op1,op2) \
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cache op1,0(a0) ; \
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nop; \
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cache op2,0(a0) ; \
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nop; \
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cache op1,0(a0)
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#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
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.set noreorder ; \
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10: doop##tag##ops ; \
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bne minaddr,maxaddr,10b ; \
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add minaddr,linesize ; \
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.set reorder
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/* finally the cache operation macros */
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#define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
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blez n,11f ; \
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addu n,kva ; \
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_align(kva, n, cacheLineSize) ; \
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_oploopn(kva, n, cacheLineSize, tag, ops) ; \
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11:
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#define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
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_mincache(n, cacheSize); \
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blez n,11f ; \
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addu n,kva ; \
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_align(kva, n, cacheLineSize) ; \
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_oploopn(kva, n, cacheLineSize, tag, ops) ; \
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11:
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#define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
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vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
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#define icacheop(kva, n, cacheSize, cacheLineSize, op) \
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icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
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.macro f_fill64 dst, offset, val
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LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
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#if LONGSIZE == 4
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LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
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#endif
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.endm
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/*
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* mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
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*/
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LEAF(mips_init_icache)
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blez a1, 9f
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mtc0 zero, CP0_TAGLO
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/* clear tag to invalidate */
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PTR_LI t0, INDEX_BASE
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PTR_ADDU t1, t0, a1
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1: cache_op Index_Store_Tag_I t0
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PTR_ADDU t0, a2
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bne t0, t1, 1b
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/* fill once, so data field parity is correct */
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PTR_LI t0, INDEX_BASE
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2: cache_op Fill t0
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PTR_ADDU t0, a2
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bne t0, t1, 2b
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/* invalidate again - prudent but not strictly neccessary */
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PTR_LI t0, INDEX_BASE
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1: cache_op Index_Store_Tag_I t0
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PTR_ADDU t0, a2
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bne t0, t1, 1b
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9: jr ra
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END(mips_init_icache)
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/*
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* mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
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*/
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LEAF(mips_init_dcache)
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blez a1, 9f
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mtc0 zero, CP0_TAGLO
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/* clear all tags */
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PTR_LI t0, INDEX_BASE
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PTR_ADDU t1, t0, a1
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1: cache_op Index_Store_Tag_D t0
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PTR_ADDU t0, a2
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bne t0, t1, 1b
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/* load from each line (in cached space) */
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PTR_LI t0, INDEX_BASE
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2: LONG_L zero, 0(t0)
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PTR_ADDU t0, a2
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bne t0, t1, 2b
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/* clear all tags */
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PTR_LI t0, INDEX_BASE
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1: cache_op Index_Store_Tag_D t0
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PTR_ADDU t0, a2
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bne t0, t1, 1b
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9: jr ra
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END(mips_init_dcache)
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/*******************************************************************************
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*
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* mips_cache_reset - low level initialisation of the primary caches
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*
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* This routine initialises the primary caches to ensure that they
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* have good parity. It must be called by the ROM before any cached locations
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* are used to prevent the possibility of data with bad parity being written to
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* memory.
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* To initialise the instruction cache it is essential that a source of data
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* with good parity is available. This routine
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* will initialise an area of memory starting at location zero to be used as
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* a source of parity.
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*
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* RETURNS: N/A
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*
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*/
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NESTED(mips_cache_reset, 0, ra)
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move RA, ra
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li t2, CONFIG_SYS_ICACHE_SIZE
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li t3, CONFIG_SYS_DCACHE_SIZE
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li t4, CONFIG_SYS_CACHELINE_SIZE
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move t5, t4
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li v0, MIPS_MAX_CACHE_SIZE
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/*
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* Now clear that much memory starting from zero.
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*/
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PTR_LI a0, CKSEG1
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PTR_ADDU a1, a0, v0
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2: PTR_ADDIU a0, 64
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f_fill64 a0, -64, zero
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bne a0, a1, 2b
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/*
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* The caches are probably in an indeterminate state,
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* so we force good parity into them by doing an
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* invalidate, load/fill, invalidate for each line.
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*/
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/*
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* Assume bottom of RAM will generate good parity for the cache.
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*/
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/*
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* Initialize the I-cache first,
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*/
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move a1, t2
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move a2, t4
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PTR_LA t7, mips_init_icache
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jalr t7
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/*
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* then initialize D-cache.
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*/
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move a1, t3
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move a2, t5
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PTR_LA t7, mips_init_dcache
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jalr t7
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jr RA
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END(mips_cache_reset)
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/*******************************************************************************
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*
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* dcache_status - get cache status
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*
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* RETURNS: 0 - cache disabled; 1 - cache enabled
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*
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*/
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LEAF(dcache_status)
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mfc0 t0, CP0_CONFIG
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li t1, CONF_CM_UNCACHED
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andi t0, t0, CONF_CM_CMASK
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move v0, zero
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beq t0, t1, 2f
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li v0, 1
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2: jr ra
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END(dcache_status)
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/*******************************************************************************
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*
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* dcache_disable - disable cache
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*
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* RETURNS: N/A
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*
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*/
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LEAF(dcache_disable)
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mfc0 t0, CP0_CONFIG
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li t1, -8
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and t0, t0, t1
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ori t0, t0, CONF_CM_UNCACHED
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mtc0 t0, CP0_CONFIG
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jr ra
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END(dcache_disable)
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/*******************************************************************************
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*
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* dcache_enable - enable cache
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*
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* RETURNS: N/A
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*
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*/
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LEAF(dcache_enable)
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mfc0 t0, CP0_CONFIG
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ori t0, CONF_CM_CMASK
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xori t0, CONF_CM_CMASK
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ori t0, CONF_CM_CACHABLE_NONCOHERENT
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mtc0 t0, CP0_CONFIG
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jr ra
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END(dcache_enable)
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#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
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/*******************************************************************************
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*
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* mips_cache_lock - lock RAM area pointed to by a0 in cache.
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*
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* RETURNS: N/A
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*
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*/
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#if defined(CONFIG_PURPLE)
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# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE/2)
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#else
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# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE)
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#endif
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.globl mips_cache_lock
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.ent mips_cache_lock
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mips_cache_lock:
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li a1, CKSEG0 - CACHE_LOCK_SIZE
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addu a0, a1
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li a2, CACHE_LOCK_SIZE
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li a3, CONFIG_SYS_CACHELINE_SIZE
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move a1, a2
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icacheop(a0,a1,a2,a3,0x1d)
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jr ra
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.end mips_cache_lock
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#endif /* CONFIG_SYS_INIT_RAM_LOCK_MIPS */
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