upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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207 lines
6.7 KiB
207 lines
6.7 KiB
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* Shengzhou Liu <Shengzhou.Liu@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/fsl_serdes.h>
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#include <asm/processor.h>
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#include "fsl_corenet2_serdes.h"
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struct serdes_config {
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u32 protocol;
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u8 lanes[SRDS_MAX_LANES];
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};
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static const struct serdes_config serdes1_cfg_tbl[] = {
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/* SerDes 1 */
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{0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} },
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{0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, PCIE4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, PCIE4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xDE, {PCIE3, PCIE3, PCIE3, PCIE3,
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PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
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{0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4,
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PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
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{0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
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{0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, PCIE1,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE4, PCIE4, PCIE4, PCIE4} },
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{0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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PCIE4, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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PCIE4, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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PCIE4, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10,
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XFI_FM1_MAC1, XFI_FM1_MAC2,
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PCIE4, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE4, PCIE4, PCIE4, PCIE4} },
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{0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
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SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
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PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
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PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
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PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE4, PCIE4, PCIE4, PCIE4} },
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{0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE4, PCIE4, PCIE4, PCIE4} },
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{0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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PCIE4, PCIE4, PCIE4, PCIE4} },
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{0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10,
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XFI_FM1_MAC1, XFI_FM1_MAC2,
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PCIE4, PCIE4, PCIE4, PCIE4} },
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{0xAB, {PCIE3, PCIE3, PCIE3, PCIE3,
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PCIE4, PCIE4, PCIE4, PCIE4} },
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{0xDA, {PCIE3, PCIE3, PCIE3, PCIE3,
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PCIE3, PCIE3, PCIE3, PCIE3} },
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{0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10,
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XFI_FM1_MAC1, XFI_FM1_MAC2,
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PCIE4, PCIE4, PCIE4, PCIE4} },
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#if defined(CONFIG_PPC_T2081)
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{0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
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PCIE4, PCIE4, PCIE4, PCIE4} },
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{0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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{0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
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#endif
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{}
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};
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#ifndef CONFIG_PPC_T2081
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static const struct serdes_config serdes2_cfg_tbl[] = {
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/* SerDes 2 */
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{0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
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{0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
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{0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
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{0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
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{0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
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{0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
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{0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },
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{0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
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{0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
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{}
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};
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#endif
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static const struct serdes_config *serdes_cfg_tbl[] = {
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serdes1_cfg_tbl,
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#ifndef CONFIG_PPC_T2081
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serdes2_cfg_tbl,
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#endif
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};
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
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{
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const struct serdes_config *ptr;
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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ptr = serdes_cfg_tbl[serdes];
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while (ptr->protocol) {
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if (ptr->protocol == cfg)
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return ptr->lanes[lane];
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ptr++;
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}
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return 0;
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}
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int is_serdes_prtcl_valid(int serdes, u32 prtcl)
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{
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int i;
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const struct serdes_config *ptr;
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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ptr = serdes_cfg_tbl[serdes];
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while (ptr->protocol) {
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if (ptr->protocol == prtcl)
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break;
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ptr++;
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}
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if (!ptr->protocol)
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return 0;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (ptr->lanes[i] != NONE)
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return 1;
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}
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return 0;
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}
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