upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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524 lines
14 KiB
524 lines
14 KiB
/*
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* Marvell PHY drivers
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* author Andy Fleming
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*/
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#include <config.h>
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#include <common.h>
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#include <phy.h>
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#define PHY_AUTONEGOTIATE_TIMEOUT 5000
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/* 88E1011 PHY Status Register */
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#define MIIM_88E1xxx_PHY_STATUS 0x11
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#define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000
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#define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000
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#define MIIM_88E1xxx_PHYSTAT_100 0x4000
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#define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000
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#define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800
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#define MIIM_88E1xxx_PHYSTAT_LINK 0x0400
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#define MIIM_88E1xxx_PHY_SCR 0x10
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#define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060
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/* 88E1111 PHY LED Control Register */
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#define MIIM_88E1111_PHY_LED_CONTROL 24
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#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
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#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
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/* 88E1111 Extended PHY Specific Control Register */
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#define MIIM_88E1111_PHY_EXT_CR 0x14
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#define MIIM_88E1111_RX_DELAY 0x80
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#define MIIM_88E1111_TX_DELAY 0x2
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/* 88E1111 Extended PHY Specific Status Register */
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#define MIIM_88E1111_PHY_EXT_SR 0x1b
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#define MIIM_88E1111_HWCFG_MODE_MASK 0xf
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#define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb
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#define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3
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#define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4
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#define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9
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#define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000
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#define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000
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#define MIIM_88E1111_COPPER 0
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#define MIIM_88E1111_FIBER 1
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/* 88E1118 PHY defines */
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#define MIIM_88E1118_PHY_PAGE 22
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#define MIIM_88E1118_PHY_LED_PAGE 3
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/* 88E1121 PHY LED Control Register */
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#define MIIM_88E1121_PHY_LED_CTRL 16
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#define MIIM_88E1121_PHY_LED_PAGE 3
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#define MIIM_88E1121_PHY_LED_DEF 0x0030
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/* 88E1121 PHY IRQ Enable/Status Register */
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#define MIIM_88E1121_PHY_IRQ_EN 18
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#define MIIM_88E1121_PHY_IRQ_STATUS 19
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#define MIIM_88E1121_PHY_PAGE 22
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/* 88E1145 Extended PHY Specific Control Register */
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#define MIIM_88E1145_PHY_EXT_CR 20
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#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
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#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
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#define MIIM_88E1145_PHY_LED_CONTROL 24
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#define MIIM_88E1145_PHY_LED_DIRECT 0x4100
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#define MIIM_88E1145_PHY_PAGE 29
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#define MIIM_88E1145_PHY_CAL_OV 30
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#define MIIM_88E1149_PHY_PAGE 29
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/* 88E1310 PHY defines */
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#define MIIM_88E1310_PHY_LED_CTRL 16
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#define MIIM_88E1310_PHY_IRQ_EN 18
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#define MIIM_88E1310_PHY_RGMII_CTRL 21
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#define MIIM_88E1310_PHY_PAGE 22
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/* Marvell 88E1011S */
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static int m88e1011s_config(struct phy_device *phydev)
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{
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/* Reset and configure the PHY */
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
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genphy_config_aneg(phydev);
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return 0;
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}
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/* Parse the 88E1011's status register for speed and duplex
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* information
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*/
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static uint m88e1xxx_parse_status(struct phy_device *phydev)
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{
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unsigned int speed;
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unsigned int mii_reg;
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mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS);
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if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) &&
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!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
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int i = 0;
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puts("Waiting for PHY realtime link");
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while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
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/* Timeout reached ? */
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if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
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puts(" TIMEOUT !\n");
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phydev->link = 0;
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break;
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}
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if ((i++ % 1000) == 0)
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putc('.');
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udelay(1000);
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mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
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MIIM_88E1xxx_PHY_STATUS);
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}
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puts(" done\n");
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udelay(500000); /* another 500 ms (results in faster booting) */
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} else {
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if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK)
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phydev->link = 1;
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else
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phydev->link = 0;
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}
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if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX)
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED;
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switch (speed) {
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case MIIM_88E1xxx_PHYSTAT_GBIT:
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phydev->speed = SPEED_1000;
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break;
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case MIIM_88E1xxx_PHYSTAT_100:
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phydev->speed = SPEED_100;
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break;
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default:
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phydev->speed = SPEED_10;
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break;
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}
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return 0;
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}
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static int m88e1011s_startup(struct phy_device *phydev)
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{
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genphy_update_link(phydev);
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m88e1xxx_parse_status(phydev);
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return 0;
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}
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/* Marvell 88E1111S */
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static int m88e1111s_config(struct phy_device *phydev)
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{
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int reg;
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int timeout;
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if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
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reg = phy_read(phydev,
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MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
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if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
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reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
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} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
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reg &= ~MIIM_88E1111_TX_DELAY;
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reg |= MIIM_88E1111_RX_DELAY;
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} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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reg &= ~MIIM_88E1111_RX_DELAY;
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reg |= MIIM_88E1111_TX_DELAY;
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}
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phy_write(phydev,
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MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
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reg = phy_read(phydev,
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MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
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reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
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if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
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reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
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else
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reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;
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phy_write(phydev,
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MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg);
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}
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if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
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reg = phy_read(phydev,
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MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
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reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
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reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
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reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
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phy_write(phydev, MDIO_DEVAD_NONE,
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MIIM_88E1111_PHY_EXT_SR, reg);
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}
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if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
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reg = phy_read(phydev,
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MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
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reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
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phy_write(phydev,
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MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
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reg = phy_read(phydev, MDIO_DEVAD_NONE,
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MIIM_88E1111_PHY_EXT_SR);
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reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
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MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
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reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
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phy_write(phydev, MDIO_DEVAD_NONE,
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MIIM_88E1111_PHY_EXT_SR, reg);
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/* soft reset */
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timeout = 1000;
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
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udelay(1000);
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reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
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while ((reg & BMCR_RESET) && --timeout) {
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udelay(1000);
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reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
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}
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if (!timeout)
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printf("%s: phy soft reset timeout\n", __func__);
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reg = phy_read(phydev, MDIO_DEVAD_NONE,
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MIIM_88E1111_PHY_EXT_SR);
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reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
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MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
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reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
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MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
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phy_write(phydev, MDIO_DEVAD_NONE,
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MIIM_88E1111_PHY_EXT_SR, reg);
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}
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/* soft reset */
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timeout = 1000;
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
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udelay(1000);
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reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
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while ((reg & BMCR_RESET) && --timeout) {
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udelay(1000);
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reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
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}
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if (!timeout)
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printf("%s: phy soft reset timeout\n", __func__);
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genphy_config_aneg(phydev);
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phy_reset(phydev);
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return 0;
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}
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/* Marvell 88E1118 */
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static int m88e1118_config(struct phy_device *phydev)
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{
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/* Change Page Number */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002);
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/* Delay RGMII TX and RX */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070);
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/* Change Page Number */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003);
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/* Adjust LED control */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e);
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/* Change Page Number */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
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genphy_config_aneg(phydev);
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phy_reset(phydev);
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return 0;
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}
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static int m88e1118_startup(struct phy_device *phydev)
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{
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/* Change Page Number */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
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genphy_update_link(phydev);
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m88e1xxx_parse_status(phydev);
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return 0;
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}
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/* Marvell 88E1121R */
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static int m88e1121_config(struct phy_device *phydev)
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{
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int pg;
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/* Configure the PHY */
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genphy_config_aneg(phydev);
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/* Switch the page to access the led register */
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pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE,
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MIIM_88E1121_PHY_LED_PAGE);
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/* Configure leds */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL,
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MIIM_88E1121_PHY_LED_DEF);
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/* Restore the page pointer */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg);
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/* Disable IRQs and de-assert interrupt */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0);
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phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS);
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return 0;
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}
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/* Marvell 88E1145 */
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static int m88e1145_config(struct phy_device *phydev)
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{
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int reg;
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/* Errata E0, E1 */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR,
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MIIM_88E1xxx_PHY_MDI_X_AUTO);
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reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR);
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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reg |= MIIM_M88E1145_RGMII_RX_DELAY |
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MIIM_M88E1145_RGMII_TX_DELAY;
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg);
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genphy_config_aneg(phydev);
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phy_reset(phydev);
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return 0;
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}
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static int m88e1145_startup(struct phy_device *phydev)
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{
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genphy_update_link(phydev);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
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MIIM_88E1145_PHY_LED_DIRECT);
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m88e1xxx_parse_status(phydev);
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return 0;
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}
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/* Marvell 88E1149S */
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static int m88e1149_config(struct phy_device *phydev)
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{
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
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genphy_config_aneg(phydev);
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phy_reset(phydev);
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return 0;
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}
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/* Marvell 88E1310 */
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static int m88e1310_config(struct phy_device *phydev)
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{
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u16 reg;
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/* LED link and activity */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
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reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
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reg = (reg & ~0xf) | 0x1;
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
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/* Set LED2/INT to INT mode, low active */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
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reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
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reg = (reg & 0x77ff) | 0x0880;
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
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/* Set RGMII delay */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
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reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
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reg |= 0x0030;
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
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/* Ensure to return to page 0 */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
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genphy_config_aneg(phydev);
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phy_reset(phydev);
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return 0;
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}
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static struct phy_driver M88E1011S_driver = {
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.name = "Marvell 88E1011S",
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.uid = 0x1410c60,
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.mask = 0xffffff0,
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.features = PHY_GBIT_FEATURES,
|
|
.config = &m88e1011s_config,
|
|
.startup = &m88e1011s_startup,
|
|
.shutdown = &genphy_shutdown,
|
|
};
|
|
|
|
static struct phy_driver M88E1111S_driver = {
|
|
.name = "Marvell 88E1111S",
|
|
.uid = 0x1410cc0,
|
|
.mask = 0xffffff0,
|
|
.features = PHY_GBIT_FEATURES,
|
|
.config = &m88e1111s_config,
|
|
.startup = &m88e1011s_startup,
|
|
.shutdown = &genphy_shutdown,
|
|
};
|
|
|
|
static struct phy_driver M88E1118_driver = {
|
|
.name = "Marvell 88E1118",
|
|
.uid = 0x1410e10,
|
|
.mask = 0xffffff0,
|
|
.features = PHY_GBIT_FEATURES,
|
|
.config = &m88e1118_config,
|
|
.startup = &m88e1118_startup,
|
|
.shutdown = &genphy_shutdown,
|
|
};
|
|
|
|
static struct phy_driver M88E1118R_driver = {
|
|
.name = "Marvell 88E1118R",
|
|
.uid = 0x1410e40,
|
|
.mask = 0xffffff0,
|
|
.features = PHY_GBIT_FEATURES,
|
|
.config = &m88e1118_config,
|
|
.startup = &m88e1118_startup,
|
|
.shutdown = &genphy_shutdown,
|
|
};
|
|
|
|
static struct phy_driver M88E1121R_driver = {
|
|
.name = "Marvell 88E1121R",
|
|
.uid = 0x1410cb0,
|
|
.mask = 0xffffff0,
|
|
.features = PHY_GBIT_FEATURES,
|
|
.config = &m88e1121_config,
|
|
.startup = &genphy_startup,
|
|
.shutdown = &genphy_shutdown,
|
|
};
|
|
|
|
static struct phy_driver M88E1145_driver = {
|
|
.name = "Marvell 88E1145",
|
|
.uid = 0x1410cd0,
|
|
.mask = 0xffffff0,
|
|
.features = PHY_GBIT_FEATURES,
|
|
.config = &m88e1145_config,
|
|
.startup = &m88e1145_startup,
|
|
.shutdown = &genphy_shutdown,
|
|
};
|
|
|
|
static struct phy_driver M88E1149S_driver = {
|
|
.name = "Marvell 88E1149S",
|
|
.uid = 0x1410ca0,
|
|
.mask = 0xffffff0,
|
|
.features = PHY_GBIT_FEATURES,
|
|
.config = &m88e1149_config,
|
|
.startup = &m88e1011s_startup,
|
|
.shutdown = &genphy_shutdown,
|
|
};
|
|
|
|
static struct phy_driver M88E1518_driver = {
|
|
.name = "Marvell 88E1518",
|
|
.uid = 0x1410dd1,
|
|
.mask = 0xffffff0,
|
|
.features = PHY_GBIT_FEATURES,
|
|
.config = &m88e1111s_config,
|
|
.startup = &m88e1011s_startup,
|
|
.shutdown = &genphy_shutdown,
|
|
};
|
|
|
|
static struct phy_driver M88E1310_driver = {
|
|
.name = "Marvell 88E1310",
|
|
.uid = 0x01410e90,
|
|
.mask = 0xffffff0,
|
|
.features = PHY_GBIT_FEATURES,
|
|
.config = &m88e1310_config,
|
|
.startup = &m88e1011s_startup,
|
|
.shutdown = &genphy_shutdown,
|
|
};
|
|
|
|
int phy_marvell_init(void)
|
|
{
|
|
phy_register(&M88E1310_driver);
|
|
phy_register(&M88E1149S_driver);
|
|
phy_register(&M88E1145_driver);
|
|
phy_register(&M88E1121R_driver);
|
|
phy_register(&M88E1118_driver);
|
|
phy_register(&M88E1118R_driver);
|
|
phy_register(&M88E1111S_driver);
|
|
phy_register(&M88E1011S_driver);
|
|
phy_register(&M88E1518_driver);
|
|
|
|
return 0;
|
|
}
|
|
|