upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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27 lines
931 B
27 lines
931 B
/*
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* (C) Copyright 2008
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* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#define SDR0_USB0 0x0320 /* USB Control Register */
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#define CONFIG_SYS_GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO0_23 */
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#define CONFIG_SYS_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */
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#define CONFIG_SYS_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */
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#define CONFIG_SYS_GPIO1_IORST2N (0x80000000 >> (47-32)) /* GPIO1_47 */
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#define CONFIG_SYS_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */
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#define CONFIG_SYS_GPIO1_HWVER_SHIFT 4
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#define CONFIG_SYS_GPIO1_LEDUSR1 0x00000008 /* GPIO1_60 */
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#define CONFIG_SYS_GPIO1_LEDUSR2 0x00000004 /* GPIO1_61 */
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#define CONFIG_SYS_GPIO1_LEDPOST 0x00000002 /* GPIO1_62 */
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#define CONFIG_SYS_GPIO1_LEDDU 0x00000001 /* GPIO1_63 */
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#define CPLD_VERSION_MASK 0x0f
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#define PWR_INT_FLAG 0x80
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#define PWR_RDY 0x10
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#define CPLD_IRQ (32+30)
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