upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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87 lines
2.8 KiB
87 lines
2.8 KiB
/*
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* Configuation settings for the Hitachi Solution Engine 7720
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*
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* Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MS7720SE_H
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#define __MS7720SE_H
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#define CONFIG_CPU_SH7720 1
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#define CONFIG_BOOTFILE "/boot/zImage"
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#define CONFIG_LOADADDR 0x8E000000
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#define CONFIG_DISPLAY_BOARDINFO
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#undef CONFIG_SHOW_BOOT_PROGRESS
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/* MEMORY */
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#define MS7720SE_SDRAM_BASE 0x8C000000
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#define MS7720SE_FLASH_BASE_1 0xA0000000
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#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024)
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#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
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/* List of legal baudrate settings for this board */
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
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/* SCIF */
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#define CONFIG_CONS_SCIF0 1
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#define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
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#define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE
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#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
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#define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1
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#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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/* FLASH */
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#undef CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1
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#define CONFIG_SYS_MAX_FLASH_SECT 150
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_ENV_SECT_SIZE (64 * 1024)
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */
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/* PCMCIA */
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#define CONFIG_IDE_PCMCIA 1
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#define CONFIG_MARUBUN_PCCARD 1
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#define CONFIG_PCMCIA_SLOT_A 1
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#define CONFIG_SYS_IDE_MAXDEVICE 1
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#define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0
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#define CONFIG_SYS_MARUBUN_MW1 0xb8400000
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#define CONFIG_SYS_MARUBUN_MW2 0xb8500000
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#define CONFIG_SYS_MARUBUN_IO 0xb8600000
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#define CONFIG_SYS_PIO_MODE 1
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#define CONFIG_SYS_IDE_MAXBUS 1
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#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
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#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
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#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
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#define CONFIG_IDE_SWAP_IO
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#endif /* __MS7720SE_H */
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