upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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36 lines
986 B
36 lines
986 B
/*
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* Configuration for Xilinx ZynqMP zcu100
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*
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* (C) Copyright 2015 - 2016 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_ZYNQMP_ZCU100_H
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#define __CONFIG_ZYNQMP_ZCU100_H
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/* FIXME Will go away soon */
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#define CONFIG_SYS_I2C_MAX_HOPS 1
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#define CONFIG_SYS_NUM_I2C_BUSES 9
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#define CONFIG_SYS_I2C_BUSES { \
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{0, {I2C_NULL_HOP} }, \
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{0, {{I2C_MUX_PCA9548, 0x75, 0} } }, \
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{0, {{I2C_MUX_PCA9548, 0x75, 1} } }, \
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{0, {{I2C_MUX_PCA9548, 0x75, 2} } }, \
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{0, {{I2C_MUX_PCA9548, 0x75, 3} } }, \
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{0, {{I2C_MUX_PCA9548, 0x75, 4} } }, \
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{0, {{I2C_MUX_PCA9548, 0x75, 5} } }, \
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{0, {{I2C_MUX_PCA9548, 0x75, 6} } }, \
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{0, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
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}
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#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
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ZYNQMP_USB1_XHCI_BASEADDR}
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_ASIX
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#include <configs/xilinx_zynqmp.h>
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#endif /* __CONFIG_ZYNQMP_ZCU100_H */
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