upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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1003 lines
32 KiB
1003 lines
32 KiB
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* PCI.c - PCI functions */
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#include <common.h>
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#ifdef CONFIG_PCI
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#include <pci.h>
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#include "../../Marvell/include/pci.h"
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#undef DEBUG
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#undef IDE_SET_NATIVE_MODE
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static unsigned int local_buses[] = { 0, 0 };
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static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
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{0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
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{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
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};
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#ifdef CONFIG_USE_CPCIDVI
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typedef struct {
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unsigned int base;
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unsigned int init;
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} GT_CPCIDVI_ROM_T;
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static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
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#endif
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#ifdef DEBUG
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static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
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static void gt_pci_bus_mode_display (PCI_HOST host)
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{
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unsigned int mode;
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mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
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switch (mode) {
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case 0:
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printf ("PCI %d bus mode: Conventional PCI\n", host);
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break;
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case 1:
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printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
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break;
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case 2:
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printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
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break;
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case 3:
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printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
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break;
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default:
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printf ("Unknown BUS %d\n", mode);
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}
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}
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#endif
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static const unsigned int pci_p2p_configuration_reg[] = {
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PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
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};
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static const unsigned int pci_configuration_address[] = {
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PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
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};
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static const unsigned int pci_configuration_data[] = {
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PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
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PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
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};
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static const unsigned int pci_error_cause_reg[] = {
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PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
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};
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static const unsigned int pci_arbiter_control[] = {
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PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
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};
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static const unsigned int pci_address_space_en[] = {
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PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
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};
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static const unsigned int pci_snoop_control_base_0_low[] = {
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PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
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};
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static const unsigned int pci_snoop_control_top_0[] = {
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PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
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};
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static const unsigned int pci_access_control_base_0_low[] = {
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PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
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};
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static const unsigned int pci_access_control_top_0[] = {
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PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
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};
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static const unsigned int pci_scs_bank_size[2][4] = {
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{PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
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PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
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{PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
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PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
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};
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static const unsigned int pci_p2p_configuration[] = {
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PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
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};
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/********************************************************************
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* pciWriteConfigReg - Write to a PCI configuration register
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* - Make sure the GT is configured as a master before writing
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* to another device on the PCI.
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* - The function takes care of Big/Little endian conversion.
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*
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*
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* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
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* (or any other PCI device spec)
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* pciDevNum: The device number needs to be addressed.
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*
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* Configuration Address 0xCF8:
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*
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* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
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* |congif|Reserved| Bus |Device|Function|Register|00|
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* |Enable| |Number|Number| Number | Number | | <=field Name
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*
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*********************************************************************/
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void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
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unsigned int pciDevNum, unsigned int data)
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{
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volatile unsigned int DataForAddrReg;
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unsigned int functionNum;
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unsigned int busNum = 0;
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unsigned int addr;
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if (pciDevNum > 32) /* illegal device Number */
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return;
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if (pciDevNum == SELF) { /* configure our configuration space. */
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pciDevNum =
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(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
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0x1f;
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busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
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0xff0000;
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}
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functionNum = regOffset & 0x00000700;
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pciDevNum = pciDevNum << 11;
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regOffset = regOffset & 0xfc;
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DataForAddrReg =
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(regOffset | pciDevNum | functionNum | busNum) | BIT31;
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GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
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GT_REG_READ (pci_configuration_address[host], &addr);
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if (addr != DataForAddrReg)
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return;
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GT_REG_WRITE (pci_configuration_data[host], data);
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}
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/********************************************************************
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* pciReadConfigReg - Read from a PCI0 configuration register
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* - Make sure the GT is configured as a master before reading
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* from another device on the PCI.
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* - The function takes care of Big/Little endian conversion.
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* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
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* spec)
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* pciDevNum: The device number needs to be addressed.
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* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
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* cause register to make sure the data is valid
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*
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* Configuration Address 0xCF8:
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*
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* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
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* |congif|Reserved| Bus |Device|Function|Register|00|
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* |Enable| |Number|Number| Number | Number | | <=field Name
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*
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*********************************************************************/
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unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
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unsigned int pciDevNum)
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{
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volatile unsigned int DataForAddrReg;
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unsigned int data;
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unsigned int functionNum;
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unsigned int busNum = 0;
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if (pciDevNum > 32) /* illegal device Number */
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return 0xffffffff;
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if (pciDevNum == SELF) { /* configure our configuration space. */
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pciDevNum =
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(GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
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0x1f;
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busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
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0xff0000;
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}
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functionNum = regOffset & 0x00000700;
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pciDevNum = pciDevNum << 11;
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regOffset = regOffset & 0xfc;
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DataForAddrReg =
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(regOffset | pciDevNum | functionNum | busNum) | BIT31;
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GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
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GT_REG_READ (pci_configuration_address[host], &data);
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if (data != DataForAddrReg)
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return 0xffffffff;
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GT_REG_READ (pci_configuration_data[host], &data);
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return data;
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}
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/********************************************************************
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* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
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* the agent is placed on another Bus. For more
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* information read P2P in the PCI spec.
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*
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* Inputs: unsigned int regOffset - The register offset as it apears in the
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* GT spec (or any other PCI device spec).
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* unsigned int pciDevNum - The device number needs to be addressed.
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* unsigned int busNum - On which bus does the Target agent connect
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* to.
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* unsigned int data - data to be written.
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*
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* Configuration Address 0xCF8:
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*
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* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
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* |congif|Reserved| Bus |Device|Function|Register|01|
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* |Enable| |Number|Number| Number | Number | | <=field Name
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*
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* The configuration Address is configure as type-I (bits[1:0] = '01') due to
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* PCI spec referring to P2P.
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*
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*********************************************************************/
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void pciOverBridgeWriteConfigReg (PCI_HOST host,
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unsigned int regOffset,
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unsigned int pciDevNum,
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unsigned int busNum, unsigned int data)
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{
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unsigned int DataForReg;
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unsigned int functionNum;
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functionNum = regOffset & 0x00000700;
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pciDevNum = pciDevNum << 11;
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regOffset = regOffset & 0xff;
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busNum = busNum << 16;
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if (pciDevNum == SELF) { /* This board */
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DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
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} else {
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DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
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BIT31 | BIT0;
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}
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GT_REG_WRITE (pci_configuration_address[host], DataForReg);
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GT_REG_WRITE (pci_configuration_data[host], data);
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}
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/********************************************************************
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* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
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* the agent target locate on another PCI bus.
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* - Make sure the GT is configured as a master
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* before reading from another device on the PCI.
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* - The function takes care of Big/Little endian
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* conversion.
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* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
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* spec). (configuration register offset.)
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* pciDevNum: The device number needs to be addressed.
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* busNum: the Bus number where the agent is place.
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* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
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* cause register to make sure the data is valid
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*
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* Configuration Address 0xCF8:
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*
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* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
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* |congif|Reserved| Bus |Device|Function|Register|01|
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* |Enable| |Number|Number| Number | Number | | <=field Name
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*
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*********************************************************************/
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unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
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unsigned int regOffset,
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unsigned int pciDevNum,
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unsigned int busNum)
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{
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unsigned int DataForReg;
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unsigned int data;
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unsigned int functionNum;
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functionNum = regOffset & 0x00000700;
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pciDevNum = pciDevNum << 11;
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regOffset = regOffset & 0xff;
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busNum = busNum << 16;
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if (pciDevNum == SELF) { /* This board */
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DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
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} else { /* agent on another bus */
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DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
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BIT0 | BIT31;
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}
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GT_REG_WRITE (pci_configuration_address[host], DataForReg);
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GT_REG_READ (pci_configuration_data[host], &data);
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return data;
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}
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/********************************************************************
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* pciGetRegOffset - Gets the register offset for this region config.
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*
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* INPUT: Bus, Region - The bus and region we ask for its base address.
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* OUTPUT: N/A
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* RETURNS: PCI register base address
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*********************************************************************/
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static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
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{
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switch (host) {
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case PCI_HOST0:
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switch (region) {
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case PCI_IO:
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return PCI_0I_O_LOW_DECODE_ADDRESS;
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case PCI_REGION0:
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return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
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case PCI_REGION1:
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return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
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case PCI_REGION2:
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return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
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case PCI_REGION3:
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return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
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}
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case PCI_HOST1:
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switch (region) {
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case PCI_IO:
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return PCI_1I_O_LOW_DECODE_ADDRESS;
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case PCI_REGION0:
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return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
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case PCI_REGION1:
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return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
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case PCI_REGION2:
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return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
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case PCI_REGION3:
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return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
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}
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}
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return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
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}
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static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
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{
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switch (host) {
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case PCI_HOST0:
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switch (region) {
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case PCI_IO:
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return PCI_0I_O_ADDRESS_REMAP;
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case PCI_REGION0:
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return PCI_0MEMORY0_ADDRESS_REMAP;
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case PCI_REGION1:
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return PCI_0MEMORY1_ADDRESS_REMAP;
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case PCI_REGION2:
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return PCI_0MEMORY2_ADDRESS_REMAP;
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case PCI_REGION3:
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return PCI_0MEMORY3_ADDRESS_REMAP;
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}
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case PCI_HOST1:
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switch (region) {
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case PCI_IO:
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return PCI_1I_O_ADDRESS_REMAP;
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case PCI_REGION0:
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return PCI_1MEMORY0_ADDRESS_REMAP;
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case PCI_REGION1:
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return PCI_1MEMORY1_ADDRESS_REMAP;
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case PCI_REGION2:
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return PCI_1MEMORY2_ADDRESS_REMAP;
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case PCI_REGION3:
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return PCI_1MEMORY3_ADDRESS_REMAP;
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}
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}
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return PCI_0MEMORY0_ADDRESS_REMAP;
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}
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/********************************************************************
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* pciGetBaseAddress - Gets the base address of a PCI.
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* - If the PCI size is 0 then this base address has no meaning!!!
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*
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*
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* INPUT: Bus, Region - The bus and region we ask for its base address.
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* OUTPUT: N/A
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* RETURNS: PCI base address.
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*********************************************************************/
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unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
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{
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unsigned int regBase;
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unsigned int regEnd;
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unsigned int regOffset = pciGetRegOffset (host, region);
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GT_REG_READ (regOffset, ®Base);
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GT_REG_READ (regOffset + 8, ®End);
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if (regEnd <= regBase)
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return 0xffffffff; /* ERROR !!! */
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regBase = regBase << 16;
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return regBase;
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}
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bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
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unsigned int bankBase, unsigned int bankLength)
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{
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unsigned int low = 0xfff;
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unsigned int high = 0x0;
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unsigned int regOffset = pciGetRegOffset (host, region);
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unsigned int remapOffset = pciGetRemapOffset (host, region);
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if (bankLength != 0) {
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low = (bankBase >> 16) & 0xffff;
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high = ((bankBase + bankLength) >> 16) - 1;
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}
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GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
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GT_REG_WRITE (regOffset + 8, high);
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if (bankLength != 0) { /* must do AFTER writing maps */
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GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only.
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dont support upper 32
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in this driver */
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}
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return true;
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}
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unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
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{
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unsigned int low;
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unsigned int regOffset = pciGetRegOffset (host, region);
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GT_REG_READ (regOffset, &low);
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return (low & 0xffff) << 16;
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}
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unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
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{
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unsigned int low, high;
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unsigned int regOffset = pciGetRegOffset (host, region);
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GT_REG_READ (regOffset, &low);
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GT_REG_READ (regOffset + 8, &high);
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return ((high & 0xffff) + 1) << 16;
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}
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|
|
|
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/* ronen - 7/Dec/03*/
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/********************************************************************
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* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
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* Inputs: one of the PCI BAR
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*********************************************************************/
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void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
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{
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RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
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}
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void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
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{
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SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
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}
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|
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/********************************************************************
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* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
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*
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* Inputs: base and size of PCI SCS
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*********************************************************************/
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void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
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unsigned int pciDramBase, unsigned int pciDramSize)
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{
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/*ronen different function for 3rd bank. */
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unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
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pciDramBase = pciDramBase & 0xfffff000;
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pciDramBase = pciDramBase | (pciReadConfigReg (host,
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PCI_SCS_0_BASE_ADDRESS
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+ offset,
|
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SELF) & 0x00000fff);
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pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
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pciDramBase);
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if (pciDramSize == 0)
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pciDramSize++;
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GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
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gtPciEnableInternalBAR (host, bank);
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}
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|
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/********************************************************************
|
|
* pciSetRegionFeatures - This function modifys one of the 8 regions with
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* feature bits given as an input.
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* - Be advised to check the spec before modifying them.
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|
* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
|
|
* unsigned int features - See file: pci.h there are defintion for those
|
|
* region features.
|
|
* unsigned int baseAddress - The region base Address.
|
|
* unsigned int topAddress - The region top Address.
|
|
* Returns: false if one of the parameters is erroneous true otherwise.
|
|
*********************************************************************/
|
|
bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
|
|
unsigned int features, unsigned int baseAddress,
|
|
unsigned int regionLength)
|
|
{
|
|
unsigned int accessLow;
|
|
unsigned int accessHigh;
|
|
unsigned int accessTop = baseAddress + regionLength;
|
|
|
|
if (regionLength == 0) { /* close the region. */
|
|
pciDisableAccessRegion (host, region);
|
|
return true;
|
|
}
|
|
/* base Address is store is bits [11:0] */
|
|
accessLow = (baseAddress & 0xfff00000) >> 20;
|
|
/* All the features are update according to the defines in pci.h (to be on
|
|
the safe side we disable bits: [11:0] */
|
|
accessLow = accessLow | (features & 0xfffff000);
|
|
/* write to the Low Access Region register */
|
|
GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
|
|
accessLow);
|
|
|
|
accessHigh = (accessTop & 0xfff00000) >> 20;
|
|
|
|
/* write to the High Access Region register */
|
|
GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
|
|
accessHigh - 1);
|
|
return true;
|
|
}
|
|
|
|
/********************************************************************
|
|
* pciDisableAccessRegion - Disable The given Region by writing MAX size
|
|
* to its low Address and MIN size to its high Address.
|
|
*
|
|
* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
|
|
* Returns: N/A.
|
|
*********************************************************************/
|
|
void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
|
|
{
|
|
/* writing back the registers default values. */
|
|
GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
|
|
0x01001fff);
|
|
GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
|
|
}
|
|
|
|
/********************************************************************
|
|
* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
|
|
*
|
|
* Inputs: N/A
|
|
* Returns: true.
|
|
*********************************************************************/
|
|
bool pciArbiterEnable (PCI_HOST host)
|
|
{
|
|
unsigned int regData;
|
|
|
|
GT_REG_READ (pci_arbiter_control[host], ®Data);
|
|
GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
|
|
return true;
|
|
}
|
|
|
|
/********************************************************************
|
|
* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
|
|
*
|
|
* Inputs: N/A
|
|
* Returns: true
|
|
*********************************************************************/
|
|
bool pciArbiterDisable (PCI_HOST host)
|
|
{
|
|
unsigned int regData;
|
|
|
|
GT_REG_READ (pci_arbiter_control[host], ®Data);
|
|
GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
|
|
return true;
|
|
}
|
|
|
|
/********************************************************************
|
|
* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
|
|
*
|
|
* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent.
|
|
* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
|
|
* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
|
|
* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
|
|
* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
|
|
* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
|
|
* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
|
|
* Returns: true
|
|
*********************************************************************/
|
|
bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
|
|
PCI_AGENT_PRIO externalAgent0,
|
|
PCI_AGENT_PRIO externalAgent1,
|
|
PCI_AGENT_PRIO externalAgent2,
|
|
PCI_AGENT_PRIO externalAgent3,
|
|
PCI_AGENT_PRIO externalAgent4,
|
|
PCI_AGENT_PRIO externalAgent5)
|
|
{
|
|
unsigned int regData;
|
|
unsigned int writeData;
|
|
|
|
GT_REG_READ (pci_arbiter_control[host], ®Data);
|
|
writeData = (internalAgent << 7) + (externalAgent0 << 8) +
|
|
(externalAgent1 << 9) + (externalAgent2 << 10) +
|
|
(externalAgent3 << 11) + (externalAgent4 << 12) +
|
|
(externalAgent5 << 13);
|
|
regData = (regData & 0xffffc07f) | writeData;
|
|
GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
|
|
return true;
|
|
}
|
|
|
|
/********************************************************************
|
|
* pciParkingDisable - Park on last option disable, with this function you can
|
|
* disable the park on last mechanism for each agent.
|
|
* disabling this option for all agents results parking
|
|
* on the internal master.
|
|
*
|
|
* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
|
|
* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
|
|
* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
|
|
* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
|
|
* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
|
|
* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
|
|
* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
|
|
* Returns: true
|
|
*********************************************************************/
|
|
bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
|
|
PCI_AGENT_PARK externalAgent0,
|
|
PCI_AGENT_PARK externalAgent1,
|
|
PCI_AGENT_PARK externalAgent2,
|
|
PCI_AGENT_PARK externalAgent3,
|
|
PCI_AGENT_PARK externalAgent4,
|
|
PCI_AGENT_PARK externalAgent5)
|
|
{
|
|
unsigned int regData;
|
|
unsigned int writeData;
|
|
|
|
GT_REG_READ (pci_arbiter_control[host], ®Data);
|
|
writeData = (internalAgent << 14) + (externalAgent0 << 15) +
|
|
(externalAgent1 << 16) + (externalAgent2 << 17) +
|
|
(externalAgent3 << 18) + (externalAgent4 << 19) +
|
|
(externalAgent5 << 20);
|
|
regData = (regData & ~(0x7f << 14)) | writeData;
|
|
GT_REG_WRITE (pci_arbiter_control[host], regData);
|
|
return true;
|
|
}
|
|
|
|
/********************************************************************
|
|
* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
|
|
* respond to grant assertion within a window specified in
|
|
* the input value: 'brokenValue'.
|
|
*
|
|
* Inputs: unsigned char brokenValue - A value which limits the Master to hold the
|
|
* grant without asserting frame.
|
|
* Returns: Error for illegal broken value otherwise true.
|
|
*********************************************************************/
|
|
bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
|
|
{
|
|
unsigned int data;
|
|
unsigned int regData;
|
|
|
|
if (brokenValue > 0xf)
|
|
return false; /* brokenValue must be 4 bit */
|
|
data = brokenValue << 3;
|
|
GT_REG_READ (pci_arbiter_control[host], ®Data);
|
|
regData = (regData & 0xffffff87) | data;
|
|
GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
|
|
return true;
|
|
}
|
|
|
|
/********************************************************************
|
|
* pciDisableBrokenAgentDetection - This function disable the Broken agent
|
|
* Detection mechanism.
|
|
* NOTE: This operation may cause a dead lock on the
|
|
* pci0 arbitration.
|
|
*
|
|
* Inputs: N/A
|
|
* Returns: true.
|
|
*********************************************************************/
|
|
bool pciDisableBrokenAgentDetection (PCI_HOST host)
|
|
{
|
|
unsigned int regData;
|
|
|
|
GT_REG_READ (pci_arbiter_control[host], ®Data);
|
|
regData = regData & 0xfffffffd;
|
|
GT_REG_WRITE (pci_arbiter_control[host], regData);
|
|
return true;
|
|
}
|
|
|
|
/********************************************************************
|
|
* pciP2PConfig - This function set the PCI_n P2P configurate.
|
|
* For more information on the P2P read PCI spec.
|
|
*
|
|
* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
|
|
* Boundry.
|
|
* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
|
|
* Boundry.
|
|
* unsigned int busNum - The CPI bus number to which the PCI interface
|
|
* is connected.
|
|
* unsigned int devNum - The PCI interface's device number.
|
|
*
|
|
* Returns: true.
|
|
*********************************************************************/
|
|
bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
|
|
unsigned int SecondBusHigh,
|
|
unsigned int busNum, unsigned int devNum)
|
|
{
|
|
unsigned int regData;
|
|
|
|
regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
|
|
((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
|
|
GT_REG_WRITE (pci_p2p_configuration[host], regData);
|
|
return true;
|
|
}
|
|
|
|
/********************************************************************
|
|
* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
|
|
* supports Cache Coherency in the PCI_n interface.
|
|
* Inputs: region - One of the four regions.
|
|
* snoopType - There is four optional Types:
|
|
* 1. No Snoop.
|
|
* 2. Snoop to WT region.
|
|
* 3. Snoop to WB region.
|
|
* 4. Snoop & Invalidate to WB region.
|
|
* baseAddress - Base Address of this region.
|
|
* regionLength - Region length.
|
|
* Returns: false if one of the parameters is wrong otherwise return true.
|
|
*********************************************************************/
|
|
bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
|
|
PCI_SNOOP_TYPE snoopType,
|
|
unsigned int baseAddress,
|
|
unsigned int regionLength)
|
|
{
|
|
unsigned int snoopXbaseAddress;
|
|
unsigned int snoopXtopAddress;
|
|
unsigned int data;
|
|
unsigned int snoopHigh = baseAddress + regionLength;
|
|
|
|
if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
|
|
return false;
|
|
snoopXbaseAddress =
|
|
pci_snoop_control_base_0_low[host] + 0x10 * region;
|
|
snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
|
|
if (regionLength == 0) { /* closing the region */
|
|
GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
|
|
GT_REG_WRITE (snoopXtopAddress, 0);
|
|
return true;
|
|
}
|
|
baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
|
|
data = (baseAddress >> 20) | snoopType << 12;
|
|
GT_REG_WRITE (snoopXbaseAddress, data);
|
|
snoopHigh = (snoopHigh & 0xfff00000) >> 20;
|
|
GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
|
|
return true;
|
|
}
|
|
|
|
static int gt_read_config_dword (struct pci_controller *hose,
|
|
pci_dev_t dev, int offset, u32 * value)
|
|
{
|
|
int bus = PCI_BUS (dev);
|
|
|
|
if ((bus == local_buses[0]) || (bus == local_buses[1])) {
|
|
*value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
|
|
PCI_DEV (dev));
|
|
} else {
|
|
*value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
|
|
cfg_addr, offset,
|
|
PCI_DEV (dev), bus);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gt_write_config_dword (struct pci_controller *hose,
|
|
pci_dev_t dev, int offset, u32 value)
|
|
{
|
|
int bus = PCI_BUS (dev);
|
|
|
|
if ((bus == local_buses[0]) || (bus == local_buses[1])) {
|
|
pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
|
|
PCI_DEV (dev), value);
|
|
} else {
|
|
pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
|
|
offset, PCI_DEV (dev), bus,
|
|
value);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
static void gt_setup_ide (struct pci_controller *hose,
|
|
pci_dev_t dev, struct pci_config_table *entry)
|
|
{
|
|
static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
|
|
u32 bar_response, bar_value;
|
|
int bar;
|
|
|
|
for (bar = 0; bar < 6; bar++) {
|
|
/*ronen different function for 3rd bank. */
|
|
unsigned int offset =
|
|
(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
|
|
|
|
pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
|
|
0x0);
|
|
pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
|
|
&bar_response);
|
|
|
|
pciauto_region_allocate (bar_response &
|
|
PCI_BASE_ADDRESS_SPACE_IO ? hose->
|
|
pci_io : hose->pci_mem, ide_bar[bar],
|
|
&bar_value);
|
|
|
|
pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4,
|
|
bar_value);
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_USE_CPCIDVI
|
|
static void gt_setup_cpcidvi (struct pci_controller *hose,
|
|
pci_dev_t dev, struct pci_config_table *entry)
|
|
{
|
|
u32 bar_value, pci_response;
|
|
|
|
pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
|
|
pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
|
|
pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
|
|
pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value);
|
|
pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00));
|
|
pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0);
|
|
pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value);
|
|
pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01);
|
|
gt_cpcidvi_rom.base = bar_value & 0xffffff00;
|
|
gt_cpcidvi_rom.init = 1;
|
|
}
|
|
|
|
unsigned char gt_cpcidvi_in8(unsigned int offset)
|
|
{
|
|
unsigned char data;
|
|
|
|
if (gt_cpcidvi_rom.init == 0) {
|
|
return(0);
|
|
}
|
|
data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
|
|
return(data);
|
|
}
|
|
|
|
void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
|
|
{
|
|
unsigned int off;
|
|
|
|
if (gt_cpcidvi_rom.init == 0) {
|
|
return;
|
|
}
|
|
off = data;
|
|
off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
|
|
in8(off);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
|
|
/* and is curently not called *. */
|
|
#if 0
|
|
static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
|
|
{
|
|
unsigned char pin, irq;
|
|
|
|
pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
|
|
|
|
if (pin == 1) { /* only allow INT A */
|
|
irq = pci_irq_swizzle[(PCI_HOST) hose->
|
|
cfg_addr][PCI_DEV (dev)];
|
|
if (irq)
|
|
pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
struct pci_config_table gt_config_table[] = {
|
|
#ifdef CONFIG_USE_CPCIDVI
|
|
{PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA,
|
|
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi},
|
|
#endif
|
|
{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
|
|
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
|
|
{}
|
|
};
|
|
|
|
struct pci_controller pci0_hose = {
|
|
/* fixup_irq: gt_fixup_irq, */
|
|
config_table:gt_config_table,
|
|
};
|
|
|
|
struct pci_controller pci1_hose = {
|
|
/* fixup_irq: gt_fixup_irq, */
|
|
config_table:gt_config_table,
|
|
};
|
|
|
|
void pci_init_board (void)
|
|
{
|
|
unsigned int command;
|
|
#ifdef CONFIG_PCI_PNP
|
|
unsigned int bar;
|
|
#endif
|
|
#ifdef DEBUG
|
|
gt_pci_bus_mode_display (PCI_HOST0);
|
|
#endif
|
|
#ifdef CONFIG_USE_CPCIDVI
|
|
gt_cpcidvi_rom.init = 0;
|
|
gt_cpcidvi_rom.base = 0;
|
|
#endif
|
|
|
|
pci0_hose.config_table = gt_config_table;
|
|
pci1_hose.config_table = gt_config_table;
|
|
|
|
#ifdef CONFIG_USE_CPCIDVI
|
|
gt_config_table[0].config_device = gt_setup_cpcidvi;
|
|
#endif
|
|
gt_config_table[1].config_device = gt_setup_ide;
|
|
|
|
pci0_hose.first_busno = 0;
|
|
pci0_hose.last_busno = 0xff;
|
|
local_buses[0] = pci0_hose.first_busno;
|
|
|
|
/* PCI memory space */
|
|
pci_set_region (pci0_hose.regions + 0,
|
|
CONFIG_SYS_PCI0_0_MEM_SPACE,
|
|
CONFIG_SYS_PCI0_0_MEM_SPACE,
|
|
CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
|
|
|
|
/* PCI I/O space */
|
|
pci_set_region (pci0_hose.regions + 1,
|
|
CONFIG_SYS_PCI0_IO_SPACE_PCI,
|
|
CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
|
|
|
|
pci_set_ops (&pci0_hose,
|
|
pci_hose_read_config_byte_via_dword,
|
|
pci_hose_read_config_word_via_dword,
|
|
gt_read_config_dword,
|
|
pci_hose_write_config_byte_via_dword,
|
|
pci_hose_write_config_word_via_dword,
|
|
gt_write_config_dword);
|
|
pci0_hose.region_count = 2;
|
|
|
|
pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
|
|
|
|
pci_register_hose (&pci0_hose);
|
|
pciArbiterDisable(PCI_HOST0); /* on PMC modules no arbiter is used */
|
|
pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
|
|
command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
|
|
command |= PCI_COMMAND_MASTER;
|
|
pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
|
|
command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
|
|
command |= PCI_COMMAND_MEMORY;
|
|
pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
|
|
|
|
#ifdef CONFIG_PCI_PNP
|
|
pciauto_config_init(&pci0_hose);
|
|
pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
|
|
#endif
|
|
#ifdef CONFIG_PCI_SCAN_SHOW
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printf("PCI: Bus Dev VenId DevId Class Int\n");
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#endif
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pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, pci0_hose.first_busno);
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#ifdef DEBUG
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gt_pci_bus_mode_display (PCI_HOST1);
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#endif
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pci1_hose.first_busno = pci0_hose.last_busno + 1;
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pci1_hose.last_busno = 0xff;
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pci1_hose.current_busno = pci1_hose.first_busno;
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local_buses[1] = pci1_hose.first_busno;
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/* PCI memory space */
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pci_set_region (pci1_hose.regions + 0,
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CONFIG_SYS_PCI1_0_MEM_SPACE,
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CONFIG_SYS_PCI1_0_MEM_SPACE,
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CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
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/* PCI I/O space */
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pci_set_region (pci1_hose.regions + 1,
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CONFIG_SYS_PCI1_IO_SPACE_PCI,
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CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
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pci_set_ops (&pci1_hose,
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pci_hose_read_config_byte_via_dword,
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pci_hose_read_config_word_via_dword,
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gt_read_config_dword,
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pci_hose_write_config_byte_via_dword,
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pci_hose_write_config_word_via_dword,
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gt_write_config_dword);
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pci1_hose.region_count = 2;
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pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
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pci_register_hose (&pci1_hose);
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pciArbiterEnable (PCI_HOST1);
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pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
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command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
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command |= PCI_COMMAND_MASTER;
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pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
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#ifdef CONFIG_PCI_PNP
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pciauto_config_init(&pci1_hose);
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pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar);
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#endif
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pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno);
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command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
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command |= PCI_COMMAND_MEMORY;
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pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
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}
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#endif /* of CONFIG_PCI */
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