upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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155 lines
5.0 KiB
155 lines
5.0 KiB
#
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# Copyright (C) 2011-2012
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# Gerald Kerma <dreagle@doukki.net>
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# Simon Baatz <gmbnomis@gmail.com>
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# Luka Perkov <luka@openwrt.org>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Refer doc/README.kwbimage for more details about how-to configure
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# and create kirkwood boot image
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#
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# Boot Media configurations
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BOOT_FROM nand
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NAND_ECC_MODE default
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NAND_PAGE_SIZE 0x0800
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# SOC registers configuration using bootrom header extension
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
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# Configure RGMII-0 interface pad voltage to 1.8V
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DATA 0xffd100e0 0x1b1b1b9b
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# Dram initalization for SINGLE x16 CL=5 @ 400MHz
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DATA 0xffd01400 0x43000c30 # DDR Configuration register
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# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
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# bit23-14: 0x0,
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# bit24: 0x1, enable exit self refresh mode on DDR access
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# bit25: 0x1, required
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# bit29-26: 0x0,
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# bit31-30: 0x1,
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DATA 0xffd01404 0x37543000 # DDR Controller Control Low
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# bit4: 0x0, addr/cmd in smame cycle
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# bit5: 0x0, clk is driven during self refresh, we don't care for APX
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# bit6: 0x0, use recommended falling edge of clk for addr/cmd
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# bit14: 0x0, input buffer always powered up
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# bit18: 0x1, cpu lock transaction enabled
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# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
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# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
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# bit30-28: 0x3, required
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# bit31: 0x0, no additional STARTBURST delay
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DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
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# bit3-0: TRAS lsbs
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# bit7-4: TRCD
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# bit11-8: TRP
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# bit15-12: TWR
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# bit19-16: TWTR
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# bit20: TRAS msb
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# bit23-21: 0x0
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# bit27-24: TRRD
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# bit31-28: TRTP
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DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
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# bit6-0: TRFC
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# bit8-7: TR2R
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# bit10-9: TR2W
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# bit12-11: TW2W
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# bit31-13: 0x0, required
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DATA 0xffd01410 0x0000000c # DDR Address Control
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# bit1-0: 00, Cs0width (x8)
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# bit3-2: 11, Cs0size (1Gb)
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# bit5-4: 00, Cs1width (x8)
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# bit7-6: 11, Cs1size (1Gb)
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# bit9-8: 00, Cs2width (nonexistent)
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# bit11-10: 00, Cs2size (nonexistent)
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# bit13-12: 00, Cs3width (nonexistent)
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# bit15-14: 00, Cs3size (nonexistent)
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# bit16: 0, Cs0AddrSel
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# bit17: 0, Cs1AddrSel
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# bit18: 0, Cs2AddrSel
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# bit19: 0, Cs3AddrSel
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# bit31-20: 0x0, required
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DATA 0xffd01414 0x00000000 # DDR Open Pages Control
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# bit0: 0, OpenPage enabled
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# bit31-1: 0x0, required
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DATA 0xffd01418 0x00000000 # DDR Operation
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# bit3-0: 0x0, DDR cmd
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# bit31-4: 0x0, required
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DATA 0xffd0141c 0x00000c52 # DDR Mode
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# bit2-0: 0x2, BurstLen=2 required
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# bit3: 0x0, BurstType=0 required
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# bit6-4: 0x4, CL=5
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# bit7: 0x0, TestMode=0 normal
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# bit8: 0x0, DLL reset=0 normal
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# bit11-9: 0x6, auto-precharge write recovery
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# bit12: 0x0, PD must be zero
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# bit31-13: 0x0, required
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DATA 0xffd01420 0x00000040 # DDR Extended Mode
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# bit0: 0, DDR DLL enabled
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# bit1: 0, DDR drive strenght normal
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# bit2: 1, DDR ODT control lsd (disabled)
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# bit5-3: 0x0, required
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# bit6: 0, DDR ODT control msb, (disabled)
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# bit9-7: 0x0, required
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# bit10: 0, differential DQS enabled
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# bit11: 0, required
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# bit12: 0, DDR output buffer enabled
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# bit31-13: 0x0, required
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DATA 0xffd01424 0x0000f17f # DDR Controller Control High
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# bit2-0: 0x7, required
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# bit3: 0x1, MBUS Burst Chop disabled
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# bit6-4: 0x7, required
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# bit7: 0x0,
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# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
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# bit9: 0x0, no half clock cycle addition to dataout
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# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals
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# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh
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# bit15-12: 0xf, required
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# bit31-16: 0, required
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DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
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DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
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DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0
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DATA 0xffd01504 0x0ffffff1 # CS[0]n Size
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# bit0: 0x1, Window enabled
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# bit1: 0x0, Write Protect disabled
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# bit3-2: 0x0, CS0 hit selected
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# bit23-4: 0xfffff, required
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# bit31-24: 0x0f, Size (i.e. 256MB)
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DATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb
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DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled
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DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled
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DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled
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DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
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# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
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# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
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# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
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# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
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DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
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# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
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# bit3-2: 0x1, ODT1 active NEVER!
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# bit31-4: 0x0, required
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DATA 0xffd0149c 0x0000e803 # CPU ODT Control
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DATA 0xffd01480 0x00000001 # DDR Initialization Control
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# bit0: 0x1, enable DDR init upon this register write
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DATA 0xffd20134 0x66666666 # L2 RAM Timing 0 Register
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DATA 0xffd20138 0x66666666 # L2 RAM Timing 1 Register
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# End of Header extension
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DATA 0x0 0x0
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