upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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94 lines
3.7 KiB
94 lines
3.7 KiB
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_PPC_GPIO_H
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#define __ASM_PPC_GPIO_H
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/* 4xx PPC's have 2 GPIO controllers */
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#if defined(CONFIG_405EZ) || \
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defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define GPIO_GROUP_MAX 2
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#else
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#define GPIO_GROUP_MAX 1
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#endif
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/* Offsets */
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#define GPIOx_OR 0x00 /* GPIO Output Register */
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#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
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#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
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#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
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#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
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#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
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#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
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#define GPIOx_IR 0x1C /* GPIO Input Register */
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#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
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#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
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#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
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#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
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#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
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#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
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#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
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#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
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#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
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#define GPIO_OR(x) (x+GPIOx_OR) /* GPIO Output Register */
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#define GPIO_TCR(x) (x+GPIOx_TCR) /* GPIO Three-State Control Register */
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#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Select Register High or Low */
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#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
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#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
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#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
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#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
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#define GPIO0 0
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#define GPIO1 1
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#define GPIO_MAX 32
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#define GPIO_ALT1_SEL 0x40000000
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#define GPIO_ALT2_SEL 0x80000000
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#define GPIO_ALT3_SEL 0xc0000000
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#define GPIO_IN_SEL 0x40000000
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#define GPIO_MASK 0xc0000000
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#define GPIO_VAL(gpio) (0x80000000 >> (gpio))
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#ifndef __ASSEMBLY__
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typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
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typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
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typedef enum gpio_out { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t;
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typedef struct {
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unsigned long add; /* gpio core base address */
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gpio_driver_t in_out; /* Driver Setting */
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gpio_select_t alt_nb; /* Selected Alternate */
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gpio_out_t out_val;/* Default Output Value */
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} gpio_param_s;
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#endif
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void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
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void gpio_write_bit(int pin, int val);
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int gpio_read_out_bit(int pin);
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int gpio_read_in_bit(int pin);
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void gpio_set_chip_configuration(void);
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#endif /* __ASM_PPC_GPIO_H */
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