upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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403 lines
20 KiB
403 lines
20 KiB
/*
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* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Interrupt vector number definitions to ease the
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* 405 -- 440 porting pain ;-)
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*
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* NOTE: They're not all here yet ... update as needed.
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*
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*/
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#ifndef _VECNUMS_H_
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#define _VECNUMS_H_
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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/* UIC 0 */
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#define VECNUM_U0 0 /* UART 0 */
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#define VECNUM_U1 1 /* UART 1 */
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#define VECNUM_IIC0 2 /* IIC */
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#define VECNUM_KRD 3 /* Kasumi Ready for data */
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#define VECNUM_KDA 4 /* Kasumi Data Available */
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#define VECNUM_PCRW 5 /* PCI command register write */
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#define VECNUM_PPM 6 /* PCI power management */
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#define VECNUM_IIC1 7 /* IIC */
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#define VECNUM_SPI 8 /* SPI */
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#define VECNUM_EPCISER 9 /* External PCI SERR */
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#define VECNUM_MTE 10 /* MAL TXEOB */
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#define VECNUM_MRE 11 /* MAL RXEOB */
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#define VECNUM_D0 12 /* DMA channel 0 */
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#define VECNUM_D1 13 /* DMA channel 1 */
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#define VECNUM_D2 14 /* DMA channel 2 */
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#define VECNUM_D3 15 /* DMA channel 3 */
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#define VECNUM_UD0 16 /* UDMA irq 0 */
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#define VECNUM_UD1 17 /* UDMA irq 1 */
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#define VECNUM_UD2 18 /* UDMA irq 2 */
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#define VECNUM_UD3 19 /* UDMA irq 3 */
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#define VECNUM_HSB2D 20 /* USB2.0 Device */
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#define VECNUM_USBDEV 20 /* USB 1.1/USB 2.0 Device */
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#define VECNUM_OHCI1 21 /* USB2.0 Host OHCI irq 1 */
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#define VECNUM_OHCI2 22 /* USB2.0 Host OHCI irq 2 */
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#define VECNUM_EIP94 23 /* Security EIP94 */
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#define VECNUM_ETH0 24 /* Emac 0 */
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#define VECNUM_ETH1 25 /* Emac 1 */
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#define VECNUM_EHCI 26 /* USB2.0 Host EHCI */
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#define VECNUM_EIR4 27 /* External interrupt 4 */
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#define VECNUM_UIC2NC 28 /* UIC2 non-critical interrupt */
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#define VECNUM_UIC2C 29 /* UIC2 critical interrupt */
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#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
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#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
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/* UIC 1 */
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#define VECNUM_MS (32 + 0) /* MAL SERR */
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#define VECNUM_MTDE (32 + 1) /* MAL TXDE */
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#define VECNUM_MRDE (32 + 2) /* MAL RXDE */
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#define VECNUM_U2 (32 + 3) /* UART 2 */
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#define VECNUM_U3 (32 + 4) /* UART 3 */
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#define VECNUM_EBCO (32 + 5) /* EBCO interrupt status */
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#define VECNUM_NDFC (32 + 6) /* NDFC */
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#define VECNUM_KSLE (32 + 7) /* KASUMI slave error */
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#define VECNUM_CT5 (32 + 8) /* GPT compare timer 5 */
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#define VECNUM_CT6 (32 + 9) /* GPT compare timer 6 */
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#define VECNUM_PLB34I0 (32 + 10) /* PLB3X4X MIRQ0 */
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#define VECNUM_PLB34I1 (32 + 11) /* PLB3X4X MIRQ1 */
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#define VECNUM_PLB34I2 (32 + 12) /* PLB3X4X MIRQ2 */
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#define VECNUM_PLB34I3 (32 + 13) /* PLB3X4X MIRQ3 */
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#define VECNUM_PLB34I4 (32 + 14) /* PLB3X4X MIRQ4 */
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#define VECNUM_PLB34I5 (32 + 15) /* PLB3X4X MIRQ5 */
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#define VECNUM_CT0 (32 + 16) /* GPT compare timer 0 */
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#define VECNUM_CT1 (32 + 17) /* GPT compare timer 1 */
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#define VECNUM_EIR7 (32 + 18) /* External interrupt 7 */
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#define VECNUM_EIR8 (32 + 19) /* External interrupt 8 */
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#define VECNUM_EIR9 (32 + 20) /* External interrupt 9 */
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#define VECNUM_CT2 (32 + 21) /* GPT compare timer 2 */
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#define VECNUM_CT3 (32 + 22) /* GPT compare timer 3 */
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#define VECNUM_CT4 (32 + 23) /* GPT compare timer 4 */
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#define VECNUM_SRE (32 + 24) /* Serial ROM error */
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#define VECNUM_GPTDC (32 + 25) /* GPT decrementer pulse */
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#define VECNUM_RSVD0 (32 + 26) /* Reserved */
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#define VECNUM_EPCIPER (32 + 27) /* External PCI PERR */
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#define VECNUM_EIR0 (32 + 28) /* External interrupt 0 */
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#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */
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#define VECNUM_EIR1 (32 + 30) /* External interrupt 1 */
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#define VECNUM_EWU1 (32 + 31) /* Ethernet 1 wakeup */
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#define VECNUM_TXDE VECNUM_MTDE
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#define VECNUM_RXDE VECNUM_MRDE
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/* UIC 2 */
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#define VECNUM_EIR5 (64 + 0) /* External interrupt 5 */
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#define VECNUM_EIR6 (64 + 1) /* External interrupt 6 */
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#define VECNUM_OPB (64 + 2) /* OPB to PLB bridge int stat */
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#define VECNUM_EIR2 (64 + 3) /* External interrupt 2 */
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#define VECNUM_EIR3 (64 + 4) /* External interrupt 3 */
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#define VECNUM_DDR2 (64 + 5) /* DDR2 sdram */
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#define VECNUM_MCTX0 (64 + 6) /* MAl intp coalescence TX0 */
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#define VECNUM_MCTX1 (64 + 7) /* MAl intp coalescence TX1 */
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#define VECNUM_MCTR0 (64 + 8) /* MAl intp coalescence TR0 */
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#define VECNUM_MCTR1 (64 + 9) /* MAl intp coalescence TR1 */
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#elif defined(CONFIG_440SPE)
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/* UIC 0 */
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#define VECNUM_U0 0 /* UART0 */
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#define VECNUM_U1 1 /* UART1 */
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#define VECNUM_IIC0 2 /* IIC0 */
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#define VECNUM_IIC1 3 /* IIC1 */
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#define VECNUM_PIM 4 /* PCI inbound message */
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#define VECNUM_PCRW 5 /* PCI command reg write */
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#define VECNUM_PPM 6 /* PCI power management */
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#define VECNUM_MSI0 7 /* PCI MSI level 0 */
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#define VECNUM_MSI1 8 /* PCI MSI level 0 */
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#define VECNUM_MSI2 9 /* PCI MSI level 0 */
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#define VECNUM_D0 12 /* DMA channel 0 */
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#define VECNUM_D1 13 /* DMA channel 1 */
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#define VECNUM_D2 14 /* DMA channel 2 */
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#define VECNUM_D3 15 /* DMA channel 3 */
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#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
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#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
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/* UIC 1 */
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#define VECNUM_MS (32 + 1 ) /* MAL SERR */
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#define VECNUM_TXDE (32 + 2 ) /* MAL TXDE */
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#define VECNUM_RXDE (32 + 3 ) /* MAL RXDE */
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#define VECNUM_MTE (32 + 6 ) /* MAL Tx EOB */
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#define VECNUM_MRE (32 + 7 ) /* MAL Rx EOB */
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#define VECNUM_CT0 (32 + 12 ) /* GPT compare timer 0 */
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#define VECNUM_CT1 (32 + 13 ) /* GPT compare timer 1 */
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#define VECNUM_CT2 (32 + 14 ) /* GPT compare timer 2 */
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#define VECNUM_CT3 (32 + 15 ) /* GPT compare timer 3 */
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#define VECNUM_CT4 (32 + 16 ) /* GPT compare timer 4 */
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#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */
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#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */
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/* UIC 2 */
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#define VECNUM_EIR5 (64 + 24) /* External interrupt 5 */
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#define VECNUM_EIR4 (64 + 25) /* External interrupt 4 */
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#define VECNUM_EIR3 (64 + 26) /* External interrupt 3 */
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#define VECNUM_EIR2 (64 + 27) /* External interrupt 2 */
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#define VECNUM_EIR1 (64 + 28) /* External interrupt 1 */
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#define VECNUM_EIR0 (64 + 29) /* External interrupt 0 */
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#elif defined(CONFIG_440SP)
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/* UIC 0 */
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#define VECNUM_U0 0 /* UART0 */
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#define VECNUM_U1 1 /* UART1 */
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#define VECNUM_IIC0 2 /* IIC0 */
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#define VECNUM_IIC1 3 /* IIC1 */
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#define VECNUM_PIM 4 /* PCI inbound message */
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#define VECNUM_PCRW 5 /* PCI command reg write */
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#define VECNUM_PPM 6 /* PCI power management */
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#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
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#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
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/* UIC 1 */
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#define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */
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#define VECNUM_MS (32 + 1) /* MAL SERR */
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#define VECNUM_TXDE (32 + 2) /* MAL TXDE */
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#define VECNUM_RXDE (32 + 3) /* MAL RXDE */
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#define VECNUM_MTE (32 + 6) /* MAL Tx EOB */
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#define VECNUM_MRE (32 + 7) /* MAL Rx EOB */
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#define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */
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#define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */
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#define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */
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#define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */
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#define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */
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#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */
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#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */
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#elif defined(CONFIG_440)
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/* UIC 0 */
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#define VECNUM_U0 0 /* UART0 */
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#define VECNUM_U1 1 /* UART1 */
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#define VECNUM_IIC0 2 /* IIC0 */
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#define VECNUM_IIC1 3 /* IIC1 */
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#define VECNUM_PIM 4 /* PCI inbound message */
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#define VECNUM_PCRW 5 /* PCI command reg write */
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#define VECNUM_PPM 6 /* PCI power management */
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#define VECNUM_MSI0 7 /* PCI MSI level 0 */
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#define VECNUM_MSI1 8 /* PCI MSI level 0 */
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#define VECNUM_MSI2 9 /* PCI MSI level 0 */
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#define VECNUM_MTE 10 /* MAL TXEOB */
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#define VECNUM_MRE 11 /* MAL RXEOB */
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#define VECNUM_D0 12 /* DMA channel 0 */
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#define VECNUM_D1 13 /* DMA channel 1 */
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#define VECNUM_D2 14 /* DMA channel 2 */
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#define VECNUM_D3 15 /* DMA channel 3 */
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#define VECNUM_CT0 18 /* GPT compare timer 0 */
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#define VECNUM_CT1 19 /* GPT compare timer 1 */
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#define VECNUM_CT2 20 /* GPT compare timer 2 */
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#define VECNUM_CT3 21 /* GPT compare timer 3 */
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#define VECNUM_CT4 22 /* GPT compare timer 4 */
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#define VECNUM_EIR0 23 /* External interrupt 0 */
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#define VECNUM_EIR1 24 /* External interrupt 1 */
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#define VECNUM_EIR2 25 /* External interrupt 2 */
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#define VECNUM_EIR3 26 /* External interrupt 3 */
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#define VECNUM_EIR4 27 /* External interrupt 4 */
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#define VECNUM_EIR5 28 /* External interrupt 5 */
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#define VECNUM_EIR6 29 /* External interrupt 6 */
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#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
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#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
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/* UIC 1 */
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#define VECNUM_MS (32 + 0 ) /* MAL SERR */
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#define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */
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#define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */
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#define VECNUM_USBDEV (32 + 23) /* USB 1.1/USB 2.0 Device */
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#define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */
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#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */
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#else /* !defined(CONFIG_440) */
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#if defined(CONFIG_405EZ)
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#define VECNUM_D0 0 /* DMA channel 0 */
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#define VECNUM_D1 1 /* DMA channel 1 */
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#define VECNUM_D2 2 /* DMA channel 2 */
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#define VECNUM_D3 3 /* DMA channel 3 */
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#define VECNUM_1588 4 /* IEEE 1588 network synchronization */
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#define VECNUM_U0 5 /* UART0 */
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#define VECNUM_U1 6 /* UART1 */
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#define VECNUM_CAN0 7 /* CAN 0 */
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#define VECNUM_CAN1 8 /* CAN 1 */
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#define VECNUM_SPI 9 /* SPI */
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#define VECNUM_IIC0 10 /* I2C */
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#define VECNUM_CHT0 11 /* Chameleon timer high pri interrupt */
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#define VECNUM_CHT1 12 /* Chameleon timer high pri interrupt */
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#define VECNUM_USBH1 13 /* USB Host 1 */
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#define VECNUM_USBH2 14 /* USB Host 2 */
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#define VECNUM_USBDEV 15 /* USB Device */
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#define VECNUM_ETH0 16 /* 10/100 Ethernet interrupt status */
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#define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */
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#define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */
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#define VECNUM_MS 18 /* MAL_SERR_INT */
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#define VECNUM_TXDE 18 /* MAL_TXDE_INT */
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#define VECNUM_RXDE 18 /* MAL_RXDE_INT */
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#define VECNUM_MTE 19 /* MAL TXEOB */
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#define VECNUM_MTE1 20 /* MAL TXEOB1 */
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#define VECNUM_MRE 21 /* MAL RXEOB */
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#define VECNUM_NAND 22 /* NAND Flash controller */
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#define VECNUM_ADC 23 /* ADC */
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#define VECNUM_DAC 24 /* DAC */
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#define VECNUM_OPB2PLB 25 /* OPB to PLB bridge interrupt */
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#define VECNUM_RESERVED0 26 /* Reserved */
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#define VECNUM_EIR0 27 /* External interrupt 0 */
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#define VECNUM_EIR1 28 /* External interrupt 1 */
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#define VECNUM_EIR2 29 /* External interrupt 2 */
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#define VECNUM_EIR3 30 /* External interrupt 3 */
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#define VECNUM_EIR4 31 /* External interrupt 4 */
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#elif defined(CONFIG_405EX)
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/* UIC 0 */
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#define VECNUM_U0 00
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#define VECNUM_U1 01
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#define VECNUM_IIC0 02
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#define VECNUM_PKA 03
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#define VECNUM_TRNG 04
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#define VECNUM_EBM 05
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#define VECNUM_BGI 06
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#define VECNUM_IIC1 07
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#define VECNUM_SPI 08
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#define VECNUM_EIR0 09
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#define VECNUM_MTE 10 /* MAL Tx EOB */
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#define VECNUM_MRE 11 /* MAL Rx EOB */
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#define VECNUM_DMA0 12
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#define VECNUM_DMA1 13
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#define VECNUM_DMA2 14
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#define VECNUM_DMA3 15
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#define VECNUM_PCIE0AL 16
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#define VECNUM_PCIE0VPD 17
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#define VECNUM_RPCIE0HRST 18
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#define VECNUM_FPCIE0HRST 19
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#define VECNUM_PCIE0TCR 20
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#define VECNUM_PCIEMSI0 21
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#define VECNUM_PCIEMSI1 22
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#define VECNUM_SECURITY 23
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#define VECNUM_ETH0 24
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#define VECNUM_ETH1 25
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#define VECNUM_PCIEMSI2 26
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#define VECNUM_EIR4 27
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#define VECNUM_UIC2NC 28
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#define VECNUM_UIC2C 29
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#define VECNUM_UIC1NC 30
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#define VECNUM_UIC1C 31
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/* UIC 1 */
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#define VECNUM_MS (32 + 00) /* MAL SERR */
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#define VECNUM_TXDE (32 + 01) /* MAL TXDE */
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#define VECNUM_RXDE (32 + 02) /* MAL RXDE */
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#define VECNUM_PCIE0BMVC0 (32 + 03)
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#define VECNUM_PCIE0DCRERR (32 + 04)
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#define VECNUM_EBC (32 + 05)
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#define VECNUM_NDFC (32 + 06)
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#define VECNUM_PCEI1DCRERR (32 + 07)
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#define VECNUM_CT8 (32 + 08)
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#define VECNUM_CT9 (32 + 09)
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#define VECNUM_PCIE1AL (32 + 10)
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#define VECNUM_PCIE1VPD (32 + 11)
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#define VECNUM_RPCE1HRST (32 + 12)
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#define VECNUM_FPCE1HRST (32 + 13)
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#define VECNUM_PCIE1TCR (32 + 14)
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#define VECNUM_PCIE1VC0 (32 + 15)
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#define VECNUM_CT3 (32 + 16)
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#define VECNUM_CT4 (32 + 17)
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#define VECNUM_EIR7 (32 + 18)
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#define VECNUM_EIR8 (32 + 19)
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#define VECNUM_EIR9 (32 + 20)
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#define VECNUM_CT5 (32 + 21)
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#define VECNUM_CT6 (32 + 22)
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#define VECNUM_CT7 (32 + 23)
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#define VECNUM_SROM (32 + 24) /* SERIAL ROM */
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#define VECNUM_GPTDECPULS (32 + 25) /* GPT Decrement pulse */
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#define VECNUM_EIR2 (32 + 26)
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#define VECNUM_EIR5 (32 + 27)
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#define VECNUM_EIR6 (32 + 28)
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#define VECNUM_EMAC0WAKE (32 + 29)
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#define VECNUM_EIR1 (32 + 30)
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#define VECNUM_EMAC1WAKE (32 + 31)
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/* UIC 2 */
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#define VECNUM_PCIE0INTA (64 + 00) /* PCIE0 INTA */
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#define VECNUM_PCIE0INTB (64 + 01) /* PCIE0 INTB */
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#define VECNUM_PCIE0INTC (64 + 02) /* PCIE0 INTC */
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#define VECNUM_PCIE0INTD (64 + 03) /* PCIE0 INTD */
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#define VECNUM_EIR3 (64 + 04) /* External IRQ 3 */
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#define VECNUM_DDRMCUE (64 + 05)
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#define VECNUM_DDRMCCE (64 + 06)
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#define VECNUM_MALINTCOATX0 (64 + 07) /* Interrupt coalecence TX0 */
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#define VECNUM_MALINTCOATX1 (64 + 08) /* Interrupt coalecence TX1 */
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#define VECNUM_MALINTCOARX0 (64 + 09) /* Interrupt coalecence RX0 */
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#define VECNUM_MALINTCOARX1 (64 + 10) /* Interrupt coalecence RX1 */
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#define VECNUM_PCIE1INTA (64 + 11) /* PCIE0 INTA */
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#define VECNUM_PCIE1INTB (64 + 12) /* PCIE0 INTB */
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#define VECNUM_PCIE1INTC (64 + 13) /* PCIE0 INTC */
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#define VECNUM_PCIE1INTD (64 + 14) /* PCIE0 INTD */
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#define VECNUM_RPCIEMSI2 (64 + 15) /* MSI level 2 */
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#define VECNUM_PCIEMSI3 (64 + 16) /* MSI level 2 */
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#define VECNUM_PCIEMSI4 (64 + 17) /* MSI level 2 */
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#define VECNUM_PCIEMSI5 (64 + 18) /* MSI level 2 */
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#define VECNUM_PCIEMSI6 (64 + 19) /* MSI level 2 */
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#define VECNUM_PCIEMSI7 (64 + 20) /* MSI level 2 */
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#define VECNUM_PCIEMSI8 (64 + 21) /* MSI level 2 */
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#define VECNUM_PCIEMSI9 (64 + 22) /* MSI level 2 */
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#define VECNUM_PCIEMSI10 (64 + 23) /* MSI level 2 */
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#define VECNUM_PCIEMSI11 (64 + 24) /* MSI level 2 */
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#define VECNUM_PCIEMSI12 (64 + 25) /* MSI level 2 */
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#define VECNUM_PCIEMSI13 (64 + 26) /* MSI level 2 */
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#define VECNUM_PCIEMSI14 (64 + 27) /* MSI level 2 */
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#define VECNUM_PCIEMSI15 (64 + 28) /* MSI level 2 */
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#define VECNUM_PLB4XAHB (64 + 29) /* PLBxAHB bridge */
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#define VECNUM_USBWAKE (64 + 30) /* USB wakup */
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#define VECNUM_USBOTG (64 + 31) /* USB OTG */
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#else /* !CONFIG_405EZ */
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#define VECNUM_U0 0 /* UART0 */
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#define VECNUM_U1 1 /* UART1 */
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#define VECNUM_D0 5 /* DMA channel 0 */
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#define VECNUM_D1 6 /* DMA channel 1 */
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#define VECNUM_D2 7 /* DMA channel 2 */
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#define VECNUM_D3 8 /* DMA channel 3 */
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#define VECNUM_EWU0 9 /* Ethernet wakeup */
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#define VECNUM_MS 10 /* MAL SERR */
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#define VECNUM_MTE 11 /* MAL TXEOB */
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#define VECNUM_MRE 12 /* MAL RXEOB */
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#define VECNUM_TXDE 13 /* MAL TXDE */
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#define VECNUM_RXDE 14 /* MAL RXDE */
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#define VECNUM_ETH0 15 /* Ethernet interrupt status */
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#define VECNUM_EIR0 25 /* External interrupt 0 */
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#define VECNUM_EIR1 26 /* External interrupt 1 */
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#define VECNUM_EIR2 27 /* External interrupt 2 */
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#define VECNUM_EIR3 28 /* External interrupt 3 */
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#define VECNUM_EIR4 29 /* External interrupt 4 */
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#define VECNUM_EIR5 30 /* External interrupt 5 */
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#define VECNUM_EIR6 31 /* External interrupt 6 */
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#endif /* defined(CONFIG_405EZ) */
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#endif /* defined(CONFIG_440) */
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#endif /* _VECNUMS_H_ */
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