upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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43 lines
1.5 KiB
43 lines
1.5 KiB
GPIO via CREG (control registers) driver
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31 9 7 5 0 < bit number
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[ not used | gpio-1 | gpio-0 | <-shift-> ] < 32 bit register
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^ ^
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write 0x2 == set output to "1" (activate)
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write 0x3 == set output to "0" (deactivate)
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Required properties:
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- compatible : "snps,creg-gpio"
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- reg : Exactly one register range with length 0x4.
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- #gpio-cells : Should be one - the pin number.
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- gpio-controller : Marks the device node as a GPIO controller.
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- gpio-count: Number of GPIO pins.
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- gpio-bit-per-line: Number of bits per gpio line (see picture).
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- gpio-first-shift: Shift (in bits) of the first GPIO field in register
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(see picture).
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- gpio-activate-val: Value should be set in corresponding field to set
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output to "1" (see picture). Applied to all GPIO ports.
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- gpio-deactivate-val: Value should be set in corresponding field to set
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output to "0" (see picture). Applied to all GPIO ports.
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Optional properties:
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- gpio-bank-name: name of bank (as default driver name is used is used)
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- gpio-default-val: array of default output values (must me 0 or 1)
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Example (see picture):
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gpio: gpio@f00014b0 {
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compatible = "snps,creg-gpio";
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reg = <0xf00014b0 0x4>;
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gpio-controller;
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#gpio-cells = <1>;
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gpio-bank-name = "hsdk-spi-cs";
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gpio-count = <2>;
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gpio-first-shift = <5>;
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gpio-bit-per-line = <2>;
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gpio-activate-val = <2>;
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gpio-deactivate-val = <3>;
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gpio-default-val = <1 1>;
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};
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