upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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356 lines
12 KiB
356 lines
12 KiB
/*
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*(C) Copyright 2005-2008 Netstal Maschinen AG
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* Niklaus Giger (Niklaus.Giger@netstal.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* hcu4.h - configuration for HCU4 board (similar to hcu5.h)
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_HCU4 1 /* Board is HCU4 */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_405GP 1
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#define CONFIG_4xx 1
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
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#define CFG_MONITOR_BASE TEXT_BASE
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/* ... with on-chip memory here (4KBytes) */
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#define CFG_OCM_DATA_ADDR 0xF4000000
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#define CFG_OCM_DATA_SIZE 0x00001000
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/* Do not set up locked dcache as init ram. */
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#undef CFG_INIT_DCACHE_CS
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/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
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#define CFG_TEMP_STACK_OCM 1
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#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* OCM */
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#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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/*
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* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
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* If CFG_405_UART_ERRATA_59, then UART divisor is 31.
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* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
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* The Linux BASE_BAUD define should match this configuration.
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* baseBaud = cpuClock/(uartDivisor*16)
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* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
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* set Linux BASE_BAUD to 403200.
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*/
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#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
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#define CONFIG_SERIAL_MULTI 1
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/* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */
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#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
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#define CFG_BASE_BAUD 691200
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/* Size (bytes) of interrupt driven serial port buffer.
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* Set to 0 to use polling instead of interrupts.
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* Setting to 0 will also disable RTS/CTS handshaking.
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*/
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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/* Set console baudrate to 9600 */
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#define CONFIG_BAUDRATE 9600
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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/*-----------------------------------------------------------------------
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* Flash
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*----------------------------------------------------------------------*/
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/* Use common CFI driver */
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#define CFG_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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/* board provides its own flash_init code */
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#define CONFIG_FLASH_CFI_LEGACY 1
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#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
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#define CFG_FLASH_LEGACY_512Kx8 1
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/* print 'E' for empty sector on flinfo */
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#define CFG_FLASH_EMPTY_INFO
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#undef CFG_ENV_IS_IN_NVRAM
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#define CFG_ENV_IS_IN_FLASH
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#undef CFG_ENV_IS_NOWHERE
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#ifdef CONFIG_ENV_IS_IN_EEPROM
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/* Put the environment after the SDRAM configuration */
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#define PROM_SIZE 2048
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#define CFG_ENV_OFFSET 512
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#define CFG_ENV_SIZE (PROM_SIZE-CFG_ENV_OFFSET)
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#endif
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#ifdef CFG_ENV_IS_IN_FLASH
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/* Put the environment in Flash */
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#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#endif
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/*-----------------------------------------------------------------------
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* I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
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* the first internal I2C controller of the PPC440EPx
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*----------------------------------------------------------------------*/
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#define CFG_SPD_BUS_NUM 0
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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/* This is the 7bit address of the device, not including P. */
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#define CFG_I2C_EEPROM_ADDR 0x50
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
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#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
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#define CFG_EEPROM_PAGE_WRITE_BITS 4
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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#undef CFG_I2C_MULTI_EEPROMS
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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/* Setup some board specific values for the default environment variables */
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#define CONFIG_HOSTNAME hcu4
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#define CONFIG_IPADDR 172.25.1.99
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#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
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#define CONFIG_OVERWRITE_ETHADDR_ONCE
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#define CONFIG_SERVERIP 172.25.1.3
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#define CFG_TFTP_LOADADDR 0x01000000 /* @16 MB */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"loadaddr=0x01000000\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
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"nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
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"bootm\0" \
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"rootpath=/home/diagnose/eldk/ppc_4xx\0" \
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"bootfile=/tftpboot/hcu4/uImage\0" \
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"load=tftp 100000 hcu4/u-boot.bin\0" \
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"update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;" \
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"cp.b 100000 FFFB0000 50000\0" \
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"upd=run load update\0" \
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"vx_rom=hcu4/hcu4_vx_rom\0" \
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"vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0" \
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"vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \
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" h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \
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""
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#define CONFIG_BOOTCOMMAND "run vx"
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 1 /* PHY address */
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_HAS_ETH0
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#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & desC */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IMMAP
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SDRAM
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/* SPD EEPROM (sdram speed config) disabled */
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#define CONFIG_SPD_EEPROM 1
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#define SPD_EEPROM_ADDRESS 0x50
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/* POST support */
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#define CONFIG_POST (CFG_POST_MEMORY | \
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CFG_POST_CPU | \
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CFG_POST_UART | \
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CFG_POST_I2C | \
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CFG_POST_CACHE | \
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CFG_POST_ETHER | \
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CFG_POST_SPR)
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#define CFG_POST_UART_TABLE {UART0_BASE}
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#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
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#undef CONFIG_LOGBUFFER
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#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
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#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
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/*-----------------------------------------------------------------------
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* Miscellaneous configurable options
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*----------------------------------------------------------------------*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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*/
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#define CFG_EBC_CFG 0x98400000
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/* Memory Bank 0 (Flash Bank 0) initialization */
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#define CFG_EBC_PB0AP 0x02005400
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#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
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#define CFG_EBC_PB1AP 0x03041200
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#define CFG_EBC_PB1CR 0x7009A000 /* BAS=,BS=MB,BU=R/W,BW=bit */
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#define CFG_EBC_PB2AP 0x02054500
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#define CFG_EBC_PB2CR 0x78018000 /* BAS=,BS=MB,BU=R/W,BW=bit */
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#define CFG_EBC_PB3AP 0x01840300
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#define CFG_EBC_PB3CR 0x7c0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
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#define CFG_EBC_PB4AP 0x01800300
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#define CFG_EBC_PB4CR 0x7e0ba000 /* BAS=,BS=MB,BU=R/W,BW=bit */
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#define CFG_GPIO0_OR 0xF27FFFFF /* GPIO value */
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#define CFG_GPIO0_TCR 0x7FFE0000 /* GPIO value */
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#define CFG_GPIO0_ODR 0x00E897FC /* GPIO value */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */
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/* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
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#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
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/* Configuration Port location */
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#define CONFIG_PORT_ADDR 0xF0000500
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#define CFG_HUSH_PARSER /* use "hush" command parser */
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#endif /* __CONFIG_H */
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