upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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446 lines
9.2 KiB
446 lines
9.2 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 Freescale Semiconductor
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* Copyright 2017 NXP
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*/
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#include <common.h>
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#include <malloc.h>
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#include <errno.h>
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#include <netdev.h>
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#include <fsl_ifc.h>
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#include <fsl_ddr.h>
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#include <asm/io.h>
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#include <hwconfig.h>
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#include <fdt_support.h>
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#include <linux/libfdt.h>
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#include <fsl-mc/fsl_mc.h>
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#include <environment.h>
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#include <efi_loader.h>
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#include <i2c.h>
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#include <asm/arch/mmu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/ppa.h>
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#include <fsl_sec.h>
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#ifdef CONFIG_FSL_QIXIS
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#include "../common/qixis.h"
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#include "ls2080ardb_qixis.h"
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#endif
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#include "../common/vid.h"
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#define PIN_MUX_SEL_SDHC 0x00
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#define PIN_MUX_SEL_DSPI 0x0a
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#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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MUX_TYPE_SDHC,
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MUX_TYPE_DSPI,
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};
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unsigned long long get_qixis_addr(void)
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{
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unsigned long long addr;
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if (gd->flags & GD_FLG_RELOC)
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addr = QIXIS_BASE_PHYS;
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else
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addr = QIXIS_BASE_PHYS_EARLY;
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/*
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* IFC address under 256MB is mapped to 0x30000000, any address above
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* is mapped to 0x5_10000000 up to 4GB.
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*/
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addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
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return addr;
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}
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int checkboard(void)
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{
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#ifdef CONFIG_FSL_QIXIS
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u8 sw;
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#endif
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char buf[15];
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cpu_name(buf);
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printf("Board: %s-RDB, ", buf);
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#ifdef CONFIG_TARGET_LS2081ARDB
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#ifdef CONFIG_FSL_QIXIS
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sw = QIXIS_READ(arch);
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printf("Board version: %c, ", (sw & 0xf) + 'A');
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
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switch (sw) {
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case 0:
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puts("boot from QSPI DEV#0\n");
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puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
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break;
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case 1:
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puts("boot from QSPI DEV#1\n");
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puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
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break;
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case 2:
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puts("boot from QSPI EMU\n");
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puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
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break;
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case 3:
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puts("boot from QSPI EMU\n");
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puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
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break;
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case 4:
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puts("boot from QSPI DEV#0\n");
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puts("QSPI_CSA_1 mapped to QSPI EMU\n");
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break;
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default:
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printf("invalid setting of SW%u\n", sw);
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break;
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}
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printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
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#endif
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puts("SERDES1 Reference : ");
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printf("Clock1 = 100MHz ");
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printf("Clock2 = 161.13MHz");
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#else
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#ifdef CONFIG_FSL_QIXIS
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sw = QIXIS_READ(arch);
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printf("Board Arch: V%d, ", sw >> 4);
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printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
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if (sw < 0x8)
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printf("vBank: %d\n", sw);
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else if (sw == 0x9)
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puts("NAND\n");
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else
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printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
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printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
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#endif
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puts("SERDES1 Reference : ");
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printf("Clock1 = 156.25MHz ");
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printf("Clock2 = 156.25MHz");
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#endif
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puts("\nSERDES2 Reference : ");
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printf("Clock1 = 100MHz ");
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printf("Clock2 = 100MHz\n");
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return 0;
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}
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unsigned long get_board_sys_clk(void)
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{
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#ifdef CONFIG_FSL_QIXIS
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u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
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switch (sysclk_conf & 0x0F) {
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case QIXIS_SYSCLK_83:
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return 83333333;
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case QIXIS_SYSCLK_100:
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return 100000000;
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case QIXIS_SYSCLK_125:
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return 125000000;
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case QIXIS_SYSCLK_133:
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return 133333333;
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case QIXIS_SYSCLK_150:
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return 150000000;
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case QIXIS_SYSCLK_160:
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return 160000000;
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case QIXIS_SYSCLK_166:
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return 166666666;
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}
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#endif
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return 100000000;
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}
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int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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}
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return 0;
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}
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int i2c_multiplexer_select_vid_channel(u8 channel)
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{
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return select_i2c_ch_pca9547(channel);
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}
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int config_board_mux(int ctrl_type)
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{
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#ifdef CONFIG_FSL_QIXIS
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u8 reg5;
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reg5 = QIXIS_READ(brdcfg[5]);
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switch (ctrl_type) {
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case MUX_TYPE_SDHC:
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reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
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break;
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case MUX_TYPE_DSPI:
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reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
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break;
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default:
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printf("Wrong mux interface type\n");
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return -1;
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}
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QIXIS_WRITE(brdcfg[5], reg5);
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#endif
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return 0;
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}
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int board_init(void)
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{
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#ifdef CONFIG_FSL_MC_ENET
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u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
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#endif
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init_final_memctl_regs();
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#ifdef CONFIG_ENV_IS_NOWHERE
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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#ifdef CONFIG_FSL_QIXIS
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QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
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#endif
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#ifdef CONFIG_FSL_CAAM
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sec_init();
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#endif
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#ifdef CONFIG_FSL_LS_PPA
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ppa_init();
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#endif
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#ifdef CONFIG_FSL_MC_ENET
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/* invert AQR405 IRQ pins polarity */
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out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
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#endif
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#ifdef CONFIG_FSL_CAAM
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sec_init();
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#endif
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return 0;
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}
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int board_early_init_f(void)
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{
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#ifdef CONFIG_SYS_I2C_EARLY_INIT
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i2c_early_init_f();
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#endif
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fsl_lsch3_early_init_f();
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return 0;
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}
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int misc_init_r(void)
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{
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char *env_hwconfig;
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u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
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u32 val;
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 svr = gur_in32(&gur->svr);
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val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
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env_hwconfig = env_get("hwconfig");
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if (hwconfig_f("dspi", env_hwconfig) &&
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DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
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config_board_mux(MUX_TYPE_DSPI);
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else
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config_board_mux(MUX_TYPE_SDHC);
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/*
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* LS2081ARDB RevF board has smart voltage translator
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* which needs to be programmed to enable high speed SD interface
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* by setting GPIO4_10 output to zero
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*/
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#ifdef CONFIG_TARGET_LS2081ARDB
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out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
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in_le32(GPIO4_GPDIR_ADDR)));
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out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
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in_le32(GPIO4_GPDAT_ADDR)));
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#endif
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if (hwconfig("sdhc"))
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config_board_mux(MUX_TYPE_SDHC);
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if (adjust_vdd(0))
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printf("Warning: Adjusting core voltage failed.\n");
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/*
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* Default value of board env is based on filename which is
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* ls2080ardb. Modify board env for other supported SoCs
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*/
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if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
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(SVR_SOC_VER(svr) == SVR_LS2048A))
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env_set("board", "ls2088ardb");
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else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
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(SVR_SOC_VER(svr) == SVR_LS2041A))
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env_set("board", "ls2081ardb");
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return 0;
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}
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void detail_board_ddr_info(void)
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{
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puts("\nDDR ");
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print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
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print_ddr_info(0);
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
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puts("\nDP-DDR ");
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print_size(gd->bd->bi_dram[2].size, "");
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print_ddr_info(CONFIG_DP_DDR_CTRL);
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}
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#endif
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}
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#if defined(CONFIG_ARCH_MISC_INIT)
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int arch_misc_init(void)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_FSL_MC_ENET
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void fdt_fixup_board_enet(void *fdt)
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{
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int offset;
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offset = fdt_path_offset(fdt, "/soc/fsl-mc");
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if (offset < 0)
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offset = fdt_path_offset(fdt, "/fsl-mc");
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if (offset < 0) {
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printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
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__func__, offset);
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return;
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}
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if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
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fdt_status_okay(fdt, offset);
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else
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fdt_status_fail(fdt, offset);
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}
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void board_quiesce_devices(void)
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{
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fsl_mc_ldpaa_exit(gd->bd);
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}
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#endif
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#ifdef CONFIG_OF_BOARD_SETUP
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void fsl_fdt_fixup_flash(void *fdt)
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{
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int offset;
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/*
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* IFC and QSPI are muxed on board.
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* So disable IFC node in dts if QSPI is enabled or
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* disable QSPI node in dts in case QSPI is not enabled.
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*/
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#ifdef CONFIG_FSL_QSPI
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offset = fdt_path_offset(fdt, "/soc/ifc");
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if (offset < 0)
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offset = fdt_path_offset(fdt, "/ifc");
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#else
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offset = fdt_path_offset(fdt, "/soc/quadspi");
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if (offset < 0)
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offset = fdt_path_offset(fdt, "/quadspi");
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#endif
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if (offset < 0)
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return;
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fdt_status_disabled(fdt, offset);
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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u64 base[CONFIG_NR_DRAM_BANKS];
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u64 size[CONFIG_NR_DRAM_BANKS];
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ft_cpu_setup(blob, bd);
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/* fixup DT for the two GPP DDR banks */
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base[0] = gd->bd->bi_dram[0].start;
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size[0] = gd->bd->bi_dram[0].size;
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base[1] = gd->bd->bi_dram[1].start;
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size[1] = gd->bd->bi_dram[1].size;
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#ifdef CONFIG_RESV_RAM
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/* reduce size if reserved memory is within this bank */
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if (gd->arch.resv_ram >= base[0] &&
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gd->arch.resv_ram < base[0] + size[0])
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size[0] = gd->arch.resv_ram - base[0];
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else if (gd->arch.resv_ram >= base[1] &&
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gd->arch.resv_ram < base[1] + size[1])
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size[1] = gd->arch.resv_ram - base[1];
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#endif
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fdt_fixup_memory_banks(blob, base, size, 2);
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fsl_fdt_fixup_dr_usb(blob, bd);
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fsl_fdt_fixup_flash(blob);
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#ifdef CONFIG_FSL_MC_ENET
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fdt_fixup_board_enet(blob);
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#endif
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return 0;
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}
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#endif
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void qixis_dump_switch(void)
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{
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#ifdef CONFIG_FSL_QIXIS
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int i, nr_of_cfgsw;
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QIXIS_WRITE(cms[0], 0x00);
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nr_of_cfgsw = QIXIS_READ(cms[1]);
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puts("DIP switch settings dump:\n");
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for (i = 1; i <= nr_of_cfgsw; i++) {
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QIXIS_WRITE(cms[0], i);
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printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
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}
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#endif
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}
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/*
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* Board rev C and earlier has duplicated I2C addresses for 2nd controller.
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* Both slots has 0x54, resulting 2nd slot unusable.
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*/
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void update_spd_address(unsigned int ctrl_num,
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unsigned int slot,
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unsigned int *addr)
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{
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#ifndef CONFIG_TARGET_LS2081ARDB
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#ifdef CONFIG_FSL_QIXIS
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u8 sw;
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sw = QIXIS_READ(arch);
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if ((sw & 0xf) < 0x3) {
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if (ctrl_num == 1 && slot == 0)
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*addr = SPD_EEPROM_ADDRESS4;
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else if (ctrl_num == 1 && slot == 1)
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*addr = SPD_EEPROM_ADDRESS3;
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}
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#endif
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#endif
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}
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