upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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349 lines
8.5 KiB
349 lines
8.5 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2007,2010 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*/
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#include <common.h>
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#include <hwconfig.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/fsl_mpc83xx_serdes.h>
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#include <spd_sdram.h>
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#include <tsec.h>
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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#include <fsl_esdhc.h>
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#include <fsl_mdio.h>
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#include <phy.h>
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#include "pci.h"
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#include "../common/pq-mds-pib.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
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/* Enable flash write */
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bcsr[0x9] &= ~0x04;
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/* Clear all of the interrupt of BCSR */
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bcsr[0xe] = 0xff;
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#ifdef CONFIG_FSL_SERDES
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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u32 spridr = in_be32(&immr->sysconf.spridr);
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/* we check only part num, and don't look for CPU revisions */
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switch (PARTID_NO_E(spridr)) {
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case SPR_8377:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8378:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
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FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
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break;
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case SPR_8379:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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default:
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printf("serdes not configured: unknown CPU part number: "
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"%04x\n", spridr >> 16);
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break;
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}
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#endif /* CONFIG_FSL_SERDES */
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return 0;
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}
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#ifdef CONFIG_FSL_ESDHC
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int board_mmc_init(bd_t *bd)
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{
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struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
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u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
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if (!hwconfig("esdhc"))
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return 0;
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/* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
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bcsr[0xc] |= 0x4c;
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/* Set proper bits in SICR to allow SD signals through */
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clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
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clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
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SICRH_GPIO2_E_SD | SICRH_SPI_SD);
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return fsl_esdhc_mmc_init(bd);
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}
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#endif
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#if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
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int board_eth_init(bd_t *bd)
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{
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[2];
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struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
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u32 rcwh = in_be32(&im->reset.rcwh);
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u32 tsec_mode;
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int num = 0;
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/* New line after Net: */
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printf("\n");
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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printf(CONFIG_TSEC1_NAME ": ");
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tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
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if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) {
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printf("RGMII\n");
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/* this is default, no need to fixup */
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} else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) {
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printf("SGMII\n");
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tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII;
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tsec_info[num].flags = TSEC_GIGABIT;
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} else {
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printf("unsupported PHY type\n");
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}
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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printf(CONFIG_TSEC2_NAME ": ");
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tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
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if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) {
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printf("RGMII\n");
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/* this is default, no need to fixup */
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} else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) {
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printf("SGMII\n");
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tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
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tsec_info[num].flags = TSEC_GIGABIT;
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} else {
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printf("unsupported PHY type\n");
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}
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num++;
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#endif
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bd, &mdio_info);
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return tsec_eth_init(bd, tsec_info, num);
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}
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static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
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int phy_addr)
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{
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const u32 *ph;
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int off;
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int err;
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off = fdt_path_offset(blob, alias);
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if (off < 0) {
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printf("WARNING: could not find %s alias: %s.\n", alias,
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fdt_strerror(off));
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return;
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}
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err = fdt_fixup_phy_connection(blob, off, PHY_INTERFACE_MODE_SGMII);
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if (err) {
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printf("WARNING: could not set phy-connection-type for %s: "
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"%s.\n", alias, fdt_strerror(err));
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return;
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}
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ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0);
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if (!ph) {
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printf("WARNING: could not get phy-handle for %s.\n",
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alias);
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return;
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}
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off = fdt_node_offset_by_phandle(blob, *ph);
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if (off < 0) {
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printf("WARNING: could not get phy node for %s: %s\n", alias,
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fdt_strerror(off));
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return;
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}
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phy_addr = cpu_to_fdt32(phy_addr);
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err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr));
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if (err < 0) {
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printf("WARNING: could not set phy node's reg for %s: "
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"%s.\n", alias, fdt_strerror(err));
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return;
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}
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}
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static void ft_tsec_fixup(void *blob, bd_t *bd)
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{
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struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
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u32 rcwh = in_be32(&im->reset.rcwh);
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u32 tsec_mode;
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#ifdef CONFIG_TSEC1
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tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
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if (tsec_mode == HRCWH_TSEC1M_IN_SGMII)
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__ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII);
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#endif
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#ifdef CONFIG_TSEC2
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tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
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if (tsec_mode == HRCWH_TSEC2M_IN_SGMII)
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__ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII);
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#endif
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}
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#else
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static inline void ft_tsec_fixup(void *blob, bd_t *bd) {}
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#endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */
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int board_early_init_r(void)
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{
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#ifdef CONFIG_PQ_MDS_PIB
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pib_init();
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#endif
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return 0;
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}
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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int fixed_sdram(void);
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int dram_init(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
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return -ENXIO;
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#if defined(CONFIG_SPD_EEPROM)
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msize = spd_sdram();
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#else
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msize = fixed_sdram();
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/* Initialize DDR ECC byte */
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ddr_enable_ecc(msize * 1024 * 1024);
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#endif
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/* return total bus DDR size(bytes) */
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gd->ram_size = msize * 1024 * 1024;
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return 0;
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
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u32 msize_log2 = __ilog2(msize);
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
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#if (CONFIG_SYS_DDR_SIZE != 512)
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#warning Currenly any ddr size other than 512 is not supported
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#endif
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im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
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udelay(50000);
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im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
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udelay(1000);
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im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
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udelay(1000);
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
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im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
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im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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__asm__ __volatile__("sync");
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udelay(1000);
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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udelay(2000);
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return CONFIG_SYS_DDR_SIZE;
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}
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#endif /*!CONFIG_SYS_SPD_EEPROM */
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int checkboard(void)
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{
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puts("Board: Freescale MPC837xEMDS\n");
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return 0;
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}
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#ifdef CONFIG_PCI
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int board_pci_host_broken(void)
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{
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struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
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const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST;
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/* It's always OK in case of external arbiter. */
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if (hwconfig_subarg_cmp("pci", "arbiter", "external"))
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return 0;
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if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
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return 1;
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return 0;
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}
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static void ft_pci_fixup(void *blob, bd_t *bd)
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{
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const char *status = "broken (no arbiter)";
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int off;
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int err;
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off = fdt_path_offset(blob, "pci0");
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if (off < 0) {
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printf("WARNING: could not find pci0 alias: %s.\n",
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fdt_strerror(off));
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return;
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}
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err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
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if (err) {
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printf("WARNING: could not set status for pci0: %s.\n",
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fdt_strerror(err));
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return;
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}
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}
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#endif
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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ft_tsec_fixup(blob, bd);
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fsl_fdt_fixup_dr_usb(blob, bd);
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fdt_fixup_esdhc(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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if (board_pci_host_broken())
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ft_pci_fixup(blob, bd);
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ft_pcie_fixup(blob, bd);
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#endif
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return 0;
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}
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#endif /* CONFIG_OF_BOARD_SETUP */
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