upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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504 lines
17 KiB
504 lines
17 KiB
/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
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* and Dan Malek
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*
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* Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
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*
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* This header file contains values common to all FADS family boards.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/****************************************************************************
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* Flash Memory Map as used by U-Boot:
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*
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* Start Address Length
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* +-----------------------+ 0xFE00_0000 Start of Flash -----------------
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* | | 0xFE00_0100 Reset Vector
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* + + 0xFE0?_????
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* | U-Boot code |
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* | |
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* +-----------------------+ 0xFE04_0000 (sector border)
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* | |
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* | |
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* | U-Boot environment |
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* | | ^
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* | | | U-Boot
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* +=======================+ 0xFE08_0000 (sector border) -----------------
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* | Available | | Applications
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* | ... | v
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*
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*****************************************************************************/
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_NFSBOOTCOMMAND \
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"dhcp;" \
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"setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
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"bootm"
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#define CONFIG_BOOTCOMMAND \
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"setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
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"bootm fe080000"
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#undef CONFIG_BOOTARGS
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#if !defined(CONFIG_MPC885ADS)
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#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
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#endif
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/*
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* New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
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* 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
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* motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
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* got FEC so FEC is the default.
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*/
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#ifndef CONFIG_ADS
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#undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */
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#define CONFIG_FEC_ENET /* Use FEC ethernet */
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#else /* Old ADS has not got FEC option */
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#define CONFIG_SCC1_ENET /* Use SCC1 ethernet */
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#undef CONFIG_FEC_ENET /* No FEC ethernet */
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#endif /* !CONFIG_ADS */
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#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
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#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
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#endif
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#ifdef CONFIG_FEC_ENET
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#define CFG_DISCOVER_PHY
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#define CONFIG_MII_INIT 1
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#if !defined(FADS_COMMANDS_ALREADY_DEFINED)
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ECHO
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#define CONFIG_CMD_IMMAP
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PCMCIA
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#define CONFIG_CMD_PING
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_PROMPT "=>" /* Monitor Command Prompt */
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#define CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#define CFG_LONGHELP /* #undef to save memory */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_LOAD_ADDR 0x00100000
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xFF000000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
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#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
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/*
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* 2048 SDRAM rows
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* 1000 factor s -> ms
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* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
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* 4 Number of refresh cycles per period
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* 64 Refresh cycle in ms per number of rows
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*/
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#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
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#elif defined(CONFIG_FADS) /* Old/new FADS */
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#define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */
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#else /* Old ADS */
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#define CFG_SDRAM_SIZE 0x00000000 /* No SDRAM */
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#endif
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#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
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#if (CFG_SDRAM_SIZE)
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#define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */
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#else
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#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
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#endif /* CFG_SDRAM_SIZE */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
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#ifdef CONFIG_BZIP2
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#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
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#else
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#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
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#endif /* CONFIG_BZIP2 */
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/*-----------------------------------------------------------------------
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* Flash organization
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*/
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#define CFG_FLASH_BASE CFG_MONITOR_BASE
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#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
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#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
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#define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */
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#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
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#define CFG_DIRECT_FLASH_TFTP
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#if defined(CONFIG_CMD_JFFS2)
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/*
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* JFFS2 partitions
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*
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*/
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/* No command line, one static partition, whole device */
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#undef CONFIG_JFFS2_CMDLINE
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#define CONFIG_JFFS2_DEV "nor0"
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#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
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#define CONFIG_JFFS2_PART_OFFSET 0x00000000
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/* mtdparts command line support */
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/* Note: fake mtd_id used, no linux mtd map file */
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/*
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#define CONFIG_JFFS2_CMDLINE
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#define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
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#define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
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*/
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#define CFG_JFFS2_SORT_FRAGMENTS
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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/*-----------------------------------------------------------------------
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* I2C configuration
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*/
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#if defined(CONFIG_CMD_I2C)
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
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#define CFG_I2C_SLAVE 0x7F
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF11
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#define CFG_SCCR SCCR_TBS
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/*-----------------------------------------------------------------------
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* DER - Debug Enable Register
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*-----------------------------------------------------------------------
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* Set to zero to prevent the processor from entering debug mode
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*/
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#define CFG_DER 0
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/* Because of the way the 860 starts up and assigns CS0 the entire
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* address space, we have to set the memory controller differently.
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* Normally, you write the option register first, and then enable the
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* chip select by writing the base register. For CS0, you must write
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* the base register first, followed by the option register.
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*/
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/*
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* Init Memory Controller:
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*
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* BR0/OR0 (Flash)
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* BR1/OR1 (BCSR)
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*/
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/* the other CS:s are determined by looking at parameters in BCSRx */
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#define BCSR_ADDR ((uint) 0xFF080000)
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#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
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/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
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#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */
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#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )
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/* BCSRx - Board Control and Status Registers */
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#define CFG_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */
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#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V)
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/* values according to the manual */
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#define BCSR0 ((uint) (BCSR_ADDR + 0x00))
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#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
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#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
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#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
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#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
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/*
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* (F)ADS bitvalues by Helmut Buchsbaum
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*
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* See User's Manual for a proper
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* description of the following structures
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*/
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#define BCSR0_ERB ((uint)0x80000000)
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#define BCSR0_IP ((uint)0x40000000)
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#define BCSR0_BDIS ((uint)0x10000000)
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#define BCSR0_BPS_MASK ((uint)0x0C000000)
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#define BCSR0_ISB_MASK ((uint)0x01800000)
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#define BCSR0_DBGC_MASK ((uint)0x00600000)
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#define BCSR0_DBPC_MASK ((uint)0x00180000)
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#define BCSR0_EBDF_MASK ((uint)0x00060000)
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#define BCSR1_FLASH_EN ((uint)0x80000000)
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#define BCSR1_DRAM_EN ((uint)0x40000000)
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#define BCSR1_ETHEN ((uint)0x20000000)
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#define BCSR1_IRDEN ((uint)0x10000000)
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#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
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#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
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#define BCSR1_BCSR_EN ((uint)0x02000000)
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#define BCSR1_RS232EN_1 ((uint)0x01000000)
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#define BCSR1_PCCEN ((uint)0x00800000)
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#define BCSR1_PCCVCC0 ((uint)0x00400000)
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#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
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#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
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#define BCSR1_RS232EN_2 ((uint)0x00040000)
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#define BCSR1_SDRAM_EN ((uint)0x00020000)
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#define BCSR1_PCCVCC1 ((uint)0x00010000)
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#define BCSR1_PCCVCCON BCSR1_PCCVCC0
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#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
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#define BCSR2_FLASH_PD_SHIFT 28
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#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
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#define BCSR2_DRAM_PD_SHIFT 23
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#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
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#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
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#define BCSR3_DBID_MASK ((ushort)0x3800)
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#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
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#define BCSR3_BREVNR0 ((ushort)0x0080)
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#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
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#define BCSR3_BREVN1 ((ushort)0x0008)
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#define BCSR3_BREVN2_MASK ((ushort)0x0003)
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#define BCSR4_ETHLOOP ((uint)0x80000000)
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#define BCSR4_TFPLDL ((uint)0x40000000)
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#define BCSR4_TPSQEL ((uint)0x20000000)
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#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
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#if defined(CONFIG_MPC823)
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#define BCSR4_USB_EN ((uint)0x08000000)
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#define BCSR4_USB_SPEED ((uint)0x04000000)
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#define BCSR4_VCCO ((uint)0x02000000)
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#define BCSR4_VIDEO_ON ((uint)0x00800000)
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#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
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#define BCSR4_VIDEO_RST ((uint)0x00200000)
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#define BCSR4_MODEM_EN ((uint)0x00100000)
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#define BCSR4_DATA_VOICE ((uint)0x00080000)
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#elif defined(CONFIG_MPC850)
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#define BCSR4_DATA_VOICE ((uint)0x00080000)
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#elif defined(CONFIG_MPC860SAR)
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#define BCSR4_UTOPIA_EN ((uint)0x08000000)
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#else /* MPC860T and other chips with FEC */
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#define BCSR4_FETH_EN ((uint)0x08000000)
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#define BCSR4_FETHCFG0 ((uint)0x04000000)
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#define BCSR4_FETHFDE ((uint)0x02000000)
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#define BCSR4_FETHCFG1 ((uint)0x00400000)
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#define BCSR4_FETHRST ((uint)0x00200000)
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#endif
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/* BSCR5 exists on MPC86xADS and MPC885ADS only */
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#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
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#define BCSR5 (CFG_PHYDEV_ADDR + 0x300)
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#define BCSR5_MII2_EN 0x40
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#define BCSR5_MII2_RST 0x20
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#define BCSR5_T1_RST 0x10
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#define BCSR5_ATM155_RST 0x08
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#define BCSR5_ATM25_RST 0x04
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#define BCSR5_MII1_EN 0x02
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#define BCSR5_MII1_RST 0x01
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/* We don't use the 8259.
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*/
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#define NR_8259_INTS 0
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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*-----------------------------------------------------------------------
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*/
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#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
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#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
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#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
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#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_IO_ADDR (0xEC000000)
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#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_MAC_PARTITION 1
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#define CONFIG_DOS_PARTITION 1
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#define CONFIG_ISO_PARTITION 1
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#undef CONFIG_ATAPI
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#if 0 /* does not make sense when CONFIG_CMD_IDE is not enabled, too */
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#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
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#endif
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#undef CONFIG_IDE_RESET /* reset for ide not supported */
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#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
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#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
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#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
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#define CFG_ATA_IDE0_OFFSET 0x0000
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/* Offset for data I/O */
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#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
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/* Offset for normal register accesses */
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#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
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/* Offset for alternate registers */
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#define CFG_ATA_ALT_OFFSET 0x0000
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#define CONFIG_DISK_SPINUP_TIME 1000000
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/* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */
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