upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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201 lines
5.7 KiB
201 lines
5.7 KiB
/*
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* include/configs/lager.h
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* This file is lager board configuration.
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __LAGER_H
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#define __LAGER_H
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#undef DEBUG
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#define CONFIG_ARMV7
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#define CONFIG_R8A7790
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#define CONFIG_RMOBILE
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#define CONFIG_RMOBILE_BOARD_STRING "Lager"
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#define CONFIG_SH_GPIO_PFC
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#define MACH_TYPE_LAGER 4538
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#define CONFIG_MACH_TYPE MACH_TYPE_LAGER
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#include <asm/arch/rmobile.h>
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#define CONFIG_CMD_EDITENV
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_DFL
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_RUN
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#define CONFIG_CMD_LOADS
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_BOOTZ
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#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
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#define CONFIG_CMD_FLASH
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#define CONFIG_SYS_TEXT_BASE 0x00000000
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#else
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_SPI
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#define CONFIG_SYS_TEXT_BASE 0xE8080000
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#endif
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_OF_LIBFDT
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/* #define CONFIG_OF_LIBFDT */
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#define BOARD_LATE_INIT
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#define CONFIG_BAUDRATE 38400
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTARGS ""
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#define CONFIG_VERSION_VARIABLE
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#undef CONFIG_SHOW_BOOT_PROGRESS
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_USE_ARCH_MEMSET
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#define CONFIG_USE_ARCH_MEMCPY
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#define CONFIG_TMU_TIMER
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/* STACK */
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#define CONFIG_SYS_INIT_SP_ADDR 0xE827fffc
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#define STACK_AREA_SIZE 0xC000
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#define LOW_LEVEL_MERAM_STACK \
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(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
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/* MEMORY */
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#define LAGER_SDRAM_BASE 0x40000000
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#define LAGER_SDRAM_SIZE (2048u * 1024 * 1024)
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#define LAGER_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_PBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE 512
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#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 }
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/* SCIF */
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#define CONFIG_SCIF_CONSOLE
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#define CONFIG_CONS_SCIF0
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#define SCIF0_BASE 0xe6e60000
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#undef CONFIG_SYS_CONSOLE_INFO_QUIET
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#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
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#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
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#define CONFIG_SYS_MEMTEST_START (LAGER_SDRAM_BASE)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
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504 * 1024 * 1024)
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#undef CONFIG_SYS_ALT_MEMTEST
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#undef CONFIG_SYS_MEMTEST_SCRATCH
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE
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#define CONFIG_SYS_SDRAM_BASE (LAGER_SDRAM_BASE)
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#define CONFIG_SYS_SDRAM_SIZE (LAGER_UBOOT_SDRAM_SIZE)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0)
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_MONITOR_BASE 0x00000000
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
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#define CONFIG_SYS_GBL_DATA_SIZE (256)
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
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/* USE NOR FLASH */
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
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#define CONFIG_FLASH_SHOW_PROGRESS 45
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#define CONFIG_SYS_FLASH_BASE 0x00000000
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#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
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#define CONFIG_SYS_MAX_FLASH_SECT 1024
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
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#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) }
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#define CONFIG_SYS_FLASH_ERASE_TOUT 3000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 3000
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#define CONFIG_SYS_FLASH_LOCK_TOUT 3000
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#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000
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/* ENV setting */
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#else /* CONFIG_SYS_USE_BOOT_NORFLASH */
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/* USE SPI */
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#define CONFIG_SPI
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#define CONFIG_SPI_FLASH_BAR
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#define CONFIG_SH_QSPI
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_SPANSION
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#define CONFIG_SYS_NO_FLASH
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/* ENV setting */
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_ADDR 0xC0000
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#endif
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/* Common ENV setting */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_SECT_SIZE (256 * 1024)
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#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
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#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
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/* SH Ether */
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#define CONFIG_NET_MULTI
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK
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#define CONFIG_SH_ETHER_CACHE_INVALIDATE
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_RCAR
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#define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000
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#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
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#define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000
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#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
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#define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000
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#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
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#define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000
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#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
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#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
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#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
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/* Board Clock */
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#define CONFIG_BASE_CLK_FREQ 20000000u
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#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */
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#define CONFIG_PLL1_CLK_FREQ (CONFIG_BASE_CLK_FREQ * 156 / 2)
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#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
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#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
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#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_MP_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_SYS_HZ 1000
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#endif /* __LAGER_H */
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