upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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106 lines
3.1 KiB
106 lines
3.1 KiB
/*
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* (C) Copyright 2006 Aubrey.Li, aubrey.li@analog.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#if defined(CONFIG_CMD_NAND)
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#include <nand.h>
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#define CONCAT(a,b,c,d) a ## b ## c ## d
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#define PORT(a,b) CONCAT(pPORT,a,b,)
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#ifndef CONFIG_NAND_GPIO_PORT
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#define CONFIG_NAND_GPIO_PORT F
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#endif
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/*
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* hardware specific access to control-lines
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*/
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static void bfin_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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register struct nand_chip *this = mtd->priv;
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switch (cmd) {
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case NAND_CTL_SETCLE:
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this->IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_CLE;
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break;
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case NAND_CTL_CLRCLE:
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this->IO_ADDR_W = CFG_NAND_BASE;
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break;
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case NAND_CTL_SETALE:
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this->IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_ALE;
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break;
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case NAND_CTL_CLRALE:
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this->IO_ADDR_W = CFG_NAND_BASE;
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break;
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case NAND_CTL_SETNCE:
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case NAND_CTL_CLRNCE:
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break;
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}
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this->IO_ADDR_R = this->IO_ADDR_W;
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/* Drain the writebuffer */
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SSYNC();
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}
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int bfin_device_ready(struct mtd_info *mtd)
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{
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int ret = (*PORT(CONFIG_NAND_GPIO_PORT, IO) & BFIN_NAND_READY) ? 1 : 0;
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SSYNC();
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return ret;
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}
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/*
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* Board-specific NAND initialization. The following members of the
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* argument are board-specific (per include/linux/mtd/nand.h):
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* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
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* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
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* - hwcontrol: hardwarespecific function for accesing control-lines
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* - dev_ready: hardwarespecific function for accesing device ready/busy line
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* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
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* only be provided if a hardware ECC is available
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* - eccmode: mode of ecc, see defines
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* - chip_delay: chip dependent delay for transfering data from array to
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* read regs (tR)
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* - options: various chip options. They can partly be set to inform
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* nand_scan about special functionality. See the defines for further
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* explanation
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* Members with a "?" were not set in the merged testing-NAND branch,
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* so they are not set here either.
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*/
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void board_nand_init(struct nand_chip *nand)
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{
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*PORT(CONFIG_NAND_GPIO_PORT, _FER) &= ~BFIN_NAND_READY;
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*PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) &= ~BFIN_NAND_READY;
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*PORT(CONFIG_NAND_GPIO_PORT, IO_INEN) |= BFIN_NAND_READY;
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nand->hwcontrol = bfin_hwcontrol;
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nand->eccmode = NAND_ECC_SOFT;
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nand->dev_ready = bfin_device_ready;
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nand->chip_delay = 30;
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}
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#endif
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