upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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240 lines
8.0 KiB
240 lines
8.0 KiB
/*
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* emac definitions for keystone2 devices
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _EMAC_DEFS_H_
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#define _EMAC_DEFS_H_
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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#define DEVICE_REG32_R(a) readl(a)
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#define DEVICE_REG32_W(a, v) writel(v, a)
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#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00090900)
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#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00090300)
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#define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00090100)
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#define KEYSTONE2_EMAC_GIG_ENABLE
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#define MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
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#ifdef CONFIG_SOC_K2HK
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/* MDIO module input frequency */
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#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
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/* MDIO clock output frequency */
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#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 1.0 MHz */
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#endif
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/* MII Status Register */
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#define MII_STATUS_REG 1
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#define MII_STATUS_LINK_MASK (0x4)
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/* Marvell 88E1111 PHY ID */
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#define PHY_MARVELL_88E1111 (0x01410cc0)
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#define MDIO_CONTROL_IDLE (0x80000000)
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#define MDIO_CONTROL_ENABLE (0x40000000)
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#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
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#define MDIO_CONTROL_FAULT (0x80000)
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#define MDIO_USERACCESS0_GO (0x80000000)
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#define MDIO_USERACCESS0_WRITE_READ (0x0)
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#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
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#define MDIO_USERACCESS0_ACK (0x20000000)
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#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
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#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
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#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
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#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
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#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
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#define EMAC_MIN_ETHERNET_PKT_SIZE 60
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struct mac_sl_cfg {
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u_int32_t max_rx_len; /* Maximum receive packet length. */
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u_int32_t ctl; /* Control bitfield */
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};
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/*
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* Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t
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*/
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#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES (1 << 24)
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#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES (1 << 23)
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#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES (1 << 22)
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#define GMACSL_RX_ENABLE_EXT_CTL (1 << 18)
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#define GMACSL_RX_ENABLE_GIG_FORCE (1 << 17)
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#define GMACSL_RX_ENABLE_IFCTL_B (1 << 16)
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#define GMACSL_RX_ENABLE_IFCTL_A (1 << 15)
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#define GMACSL_RX_ENABLE_CMD_IDLE (1 << 11)
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#define GMACSL_TX_ENABLE_SHORT_GAP (1 << 10)
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#define GMACSL_ENABLE_GIG_MODE (1 << 7)
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#define GMACSL_TX_ENABLE_PACE (1 << 6)
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#define GMACSL_ENABLE (1 << 5)
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#define GMACSL_TX_ENABLE_FLOW_CTL (1 << 4)
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#define GMACSL_RX_ENABLE_FLOW_CTL (1 << 3)
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#define GMACSL_ENABLE_LOOPBACK (1 << 1)
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#define GMACSL_ENABLE_FULL_DUPLEX (1 << 0)
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/*
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* DEFINTITION: function return values
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*/
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#define GMACSL_RET_OK 0
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#define GMACSL_RET_INVALID_PORT -1
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#define GMACSL_RET_WARN_RESET_INCOMPLETE -2
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#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3
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#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
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/* Register offsets */
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#define CPGMACSL_REG_ID 0x00
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#define CPGMACSL_REG_CTL 0x04
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#define CPGMACSL_REG_STATUS 0x08
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#define CPGMACSL_REG_RESET 0x0c
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#define CPGMACSL_REG_MAXLEN 0x10
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#define CPGMACSL_REG_BOFF 0x14
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#define CPGMACSL_REG_RX_PAUSE 0x18
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#define CPGMACSL_REG_TX_PAURSE 0x1c
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#define CPGMACSL_REG_EM_CTL 0x20
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#define CPGMACSL_REG_PRI 0x24
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/* Soft reset register values */
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#define CPGMAC_REG_RESET_VAL_RESET_MASK (1 << 0)
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#define CPGMAC_REG_RESET_VAL_RESET (1 << 0)
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/* Maxlen register values */
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#define CPGMAC_REG_MAXLEN_LEN 0x3fff
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/* Control bitfields */
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#define CPSW_CTL_P2_PASS_PRI_TAGGED (1 << 5)
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#define CPSW_CTL_P1_PASS_PRI_TAGGED (1 << 4)
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#define CPSW_CTL_P0_PASS_PRI_TAGGED (1 << 3)
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#define CPSW_CTL_P0_ENABLE (1 << 2)
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#define CPSW_CTL_VLAN_AWARE (1 << 1)
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#define CPSW_CTL_FIFO_LOOPBACK (1 << 0)
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#define DEVICE_CPSW_NUM_PORTS 5 /* 5 switch ports */
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#define DEVICE_CPSW_BASE (0x02090800)
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#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE /* Enable port 0 */
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#define SWITCH_MAX_PKT_SIZE 9000
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/* Register offsets */
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#define CPSW_REG_CTL 0x004
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#define CPSW_REG_STAT_PORT_EN 0x00c
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#define CPSW_REG_MAXLEN 0x040
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#define CPSW_REG_ALE_CONTROL 0x608
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#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x)*4)
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/* Register values */
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#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf
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#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000)
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#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010)
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#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3
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#define SGMII_REG_STATUS_LOCK BIT(4)
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#define SGMII_REG_STATUS_LINK BIT(0)
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#define SGMII_REG_STATUS_AUTONEG BIT(2)
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#define SGMII_REG_CONTROL_AUTONEG BIT(0)
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#define SGMII_REG_CONTROL_MASTER BIT(5)
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#define SGMII_REG_MR_ADV_ENABLE BIT(0)
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#define SGMII_REG_MR_ADV_LINK BIT(15)
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#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12)
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#define SGMII_REG_MR_ADV_GIG_MODE BIT(11)
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#define SGMII_LINK_MAC_MAC_AUTONEG 0
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#define SGMII_LINK_MAC_PHY 1
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#define SGMII_LINK_MAC_MAC_FORCED 2
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#define SGMII_LINK_MAC_FIBER 3
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#define SGMII_LINK_MAC_PHY_FORCED 4
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#define TARGET_SGMII_BASE KS2_PASS_BASE + 0x00090100
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#define TARGET_SGMII_BASE_ADDRESSES {KS2_PASS_BASE + 0x00090100, \
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KS2_PASS_BASE + 0x00090200, \
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KS2_PASS_BASE + 0x00090400, \
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KS2_PASS_BASE + 0x00090500}
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#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
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/*
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* SGMII registers
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*/
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#define SGMII_IDVER_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x000)
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#define SGMII_SRESET_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x004)
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#define SGMII_CTL_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x010)
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#define SGMII_STATUS_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x014)
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#define SGMII_MRADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x018)
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#define SGMII_LPADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x020)
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#define SGMII_TXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x030)
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#define SGMII_RXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x034)
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#define SGMII_AUXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x038)
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#define DEVICE_EMACSL_BASE(x) (KS2_PASS_BASE + 0x00090900 + (x) * 0x040)
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#define DEVICE_N_GMACSL_PORTS 4
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#define DEVICE_EMACSL_RESET_POLL_COUNT 100
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#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x604)
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#ifdef CONFIG_SOC_K2HK
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#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI 0x06060606
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#endif
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#define hw_config_streaming_switch() \
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DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, \
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DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI);
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/* EMAC MDIO Registers Structure */
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struct mdio_regs {
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dv_reg version;
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dv_reg control;
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dv_reg alive;
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dv_reg link;
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dv_reg linkintraw;
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dv_reg linkintmasked;
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u_int8_t rsvd0[8];
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dv_reg userintraw;
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dv_reg userintmasked;
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dv_reg userintmaskset;
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dv_reg userintmaskclear;
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u_int8_t rsvd1[80];
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dv_reg useraccess0;
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dv_reg userphysel0;
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dv_reg useraccess1;
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dv_reg userphysel1;
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};
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/* Ethernet MAC Registers Structure */
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struct emac_regs {
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dv_reg idver;
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dv_reg maccontrol;
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dv_reg macstatus;
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dv_reg soft_reset;
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dv_reg rx_maxlen;
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u32 rsvd0;
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dv_reg rx_pause;
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dv_reg tx_pause;
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dv_reg emcontrol;
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dv_reg pri_map;
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u32 rsvd1[6];
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};
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#define SGMII_ACCESS(port, reg) \
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*((volatile unsigned int *)(sgmiis[port] + reg))
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struct eth_priv_t {
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char int_name[32];
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int rx_flow;
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int phy_addr;
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int slave_port;
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int sgmii_link_type;
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};
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extern struct eth_priv_t eth_priv_cfg[];
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int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
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void sgmii_serdes_setup_156p25mhz(void);
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void sgmii_serdes_shutdown(void);
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#endif /* _EMAC_DEFS_H_ */
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