upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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49 lines
1.1 KiB
49 lines
1.1 KiB
/*
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* Copyright 2008 Extreme Engineering Solutions, Inc.
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*
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* This driver support NAND devices which have address lines
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* connected as ALE and CLE inputs.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <nand.h>
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#include <asm/io.h>
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/*
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* Hardware specific access to control-lines
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*/
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static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
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{
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struct nand_chip *this = mtd->priv;
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ulong IO_ADDR_W;
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if (ctrl & NAND_CTRL_CHANGE) {
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IO_ADDR_W = (ulong)this->IO_ADDR_W;
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IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE |
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CONFIG_SYS_NAND_ACTL_ALE |
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CONFIG_SYS_NAND_ACTL_NCE);
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if (ctrl & NAND_CLE)
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IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE;
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if (ctrl & NAND_ALE)
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IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE;
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if (ctrl & NAND_NCE)
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IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE;
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this->IO_ADDR_W = (void *)IO_ADDR_W;
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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int board_nand_init(struct nand_chip *nand)
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{
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nand->ecc.mode = NAND_ECC_SOFT;
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nand->cmd_ctrl = nand_addr_hwcontrol;
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nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY;
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return 0;
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}
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