upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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149 lines
3.8 KiB
149 lines
3.8 KiB
/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __DW_I2C_H_
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#define __DW_I2C_H_
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struct i2c_regs {
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u32 ic_con;
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u32 ic_tar;
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u32 ic_sar;
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u32 ic_hs_maddr;
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u32 ic_cmd_data;
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u32 ic_ss_scl_hcnt;
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u32 ic_ss_scl_lcnt;
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u32 ic_fs_scl_hcnt;
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u32 ic_fs_scl_lcnt;
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u32 ic_hs_scl_hcnt;
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u32 ic_hs_scl_lcnt;
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u32 ic_intr_stat;
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u32 ic_intr_mask;
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u32 ic_raw_intr_stat;
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u32 ic_rx_tl;
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u32 ic_tx_tl;
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u32 ic_clr_intr;
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u32 ic_clr_rx_under;
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u32 ic_clr_rx_over;
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u32 ic_clr_tx_over;
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u32 ic_clr_rd_req;
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u32 ic_clr_tx_abrt;
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u32 ic_clr_rx_done;
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u32 ic_clr_activity;
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u32 ic_clr_stop_det;
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u32 ic_clr_start_det;
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u32 ic_clr_gen_call;
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u32 ic_enable;
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u32 ic_status;
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u32 ic_txflr;
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u32 ix_rxflr;
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u32 reserved_1;
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u32 ic_tx_abrt_source;
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};
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#if !defined(IC_CLK)
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#define IC_CLK 166
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#endif
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#define NANO_TO_MICRO 1000
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/* High and low times in different speed modes (in ns) */
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#define MIN_SS_SCL_HIGHTIME 4000
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#define MIN_SS_SCL_LOWTIME 4700
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#define MIN_FS_SCL_HIGHTIME 600
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#define MIN_FS_SCL_LOWTIME 1300
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#define MIN_HS_SCL_HIGHTIME 60
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#define MIN_HS_SCL_LOWTIME 160
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/* Worst case timeout for 1 byte is kept as 2ms */
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#define I2C_BYTE_TO (CONFIG_SYS_HZ/500)
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#define I2C_STOPDET_TO (CONFIG_SYS_HZ/500)
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#define I2C_BYTE_TO_BB (I2C_BYTE_TO * 16)
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/* i2c control register definitions */
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#define IC_CON_SD 0x0040
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#define IC_CON_RE 0x0020
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#define IC_CON_10BITADDRMASTER 0x0010
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#define IC_CON_10BITADDR_SLAVE 0x0008
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#define IC_CON_SPD_MSK 0x0006
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#define IC_CON_SPD_SS 0x0002
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#define IC_CON_SPD_FS 0x0004
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#define IC_CON_SPD_HS 0x0006
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#define IC_CON_MM 0x0001
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/* i2c target address register definitions */
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#define TAR_ADDR 0x0050
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/* i2c slave address register definitions */
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#define IC_SLAVE_ADDR 0x0002
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/* i2c data buffer and command register definitions */
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#define IC_CMD 0x0100
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#define IC_STOP 0x0200
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/* i2c interrupt status register definitions */
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#define IC_GEN_CALL 0x0800
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#define IC_START_DET 0x0400
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#define IC_STOP_DET 0x0200
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#define IC_ACTIVITY 0x0100
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#define IC_RX_DONE 0x0080
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#define IC_TX_ABRT 0x0040
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#define IC_RD_REQ 0x0020
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#define IC_TX_EMPTY 0x0010
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#define IC_TX_OVER 0x0008
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#define IC_RX_FULL 0x0004
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#define IC_RX_OVER 0x0002
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#define IC_RX_UNDER 0x0001
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/* fifo threshold register definitions */
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#define IC_TL0 0x00
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#define IC_TL1 0x01
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#define IC_TL2 0x02
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#define IC_TL3 0x03
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#define IC_TL4 0x04
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#define IC_TL5 0x05
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#define IC_TL6 0x06
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#define IC_TL7 0x07
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#define IC_RX_TL IC_TL0
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#define IC_TX_TL IC_TL0
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/* i2c enable register definitions */
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#define IC_ENABLE_0B 0x0001
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/* i2c status register definitions */
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#define IC_STATUS_SA 0x0040
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#define IC_STATUS_MA 0x0020
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#define IC_STATUS_RFF 0x0010
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#define IC_STATUS_RFNE 0x0008
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#define IC_STATUS_TFE 0x0004
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#define IC_STATUS_TFNF 0x0002
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#define IC_STATUS_ACT 0x0001
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/* Speed Selection */
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#define IC_SPEED_MODE_STANDARD 1
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#define IC_SPEED_MODE_FAST 2
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#define IC_SPEED_MODE_MAX 3
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#define I2C_MAX_SPEED 3400000
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#define I2C_FAST_SPEED 400000
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#define I2C_STANDARD_SPEED 100000
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#endif /* __DW_I2C_H_ */
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