upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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235 lines
7.2 KiB
235 lines
7.2 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at>
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* B&R Industrial Automation GmbH - http://www.br-automation.com
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*
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* minimal framebuffer driver for TI's AM335x SoC to be compatible with
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* Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c)
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*
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* - supporting 16/24/32bit RGB/TFT raster Mode (not using palette)
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* - sets up LCD controller as in 'am335x_lcdpanel' struct given
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* - starts output DMA from gd->fb_base buffer
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <lcd.h>
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#include "am335x-fb.h"
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#if !defined(LCD_CNTL_BASE)
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#error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
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#endif
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#define LCDC_FMAX 200000000
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/* LCD Control Register */
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#define LCD_CLK_DIVISOR(x) ((x) << 8)
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#define LCD_RASTER_MODE 0x01
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/* LCD Clock Enable Register */
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#define LCD_CORECLKEN (0x01 << 0)
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#define LCD_LIDDCLKEN (0x01 << 1)
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#define LCD_DMACLKEN (0x01 << 2)
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/* LCD DMA Control Register */
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#define LCD_DMA_BURST_SIZE(x) ((x) << 4)
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#define LCD_DMA_BURST_1 0x0
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#define LCD_DMA_BURST_2 0x1
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#define LCD_DMA_BURST_4 0x2
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#define LCD_DMA_BURST_8 0x3
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#define LCD_DMA_BURST_16 0x4
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/* LCD Timing_0 Register */
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#define LCD_HBPLSB(x) ((((x)-1) & 0xFF) << 24)
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#define LCD_HFPLSB(x) ((((x)-1) & 0xFF) << 16)
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#define LCD_HSWLSB(x) ((((x)-1) & 0x3F) << 10)
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#define LCD_HORLSB(x) (((((x) >> 4)-1) & 0x3F) << 4)
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#define LCD_HORMSB(x) (((((x) >> 4)-1) & 0x40) >> 4)
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/* LCD Timing_1 Register */
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#define LCD_VBP(x) ((x) << 24)
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#define LCD_VFP(x) ((x) << 16)
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#define LCD_VSW(x) (((x)-1) << 10)
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#define LCD_VERLSB(x) (((x)-1) & 0x3FF)
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/* LCD Timing_2 Register */
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#define LCD_HSWMSB(x) ((((x)-1) & 0x3C0) << 21)
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#define LCD_VERMSB(x) ((((x)-1) & 0x400) << 16)
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#define LCD_HBPMSB(x) ((((x)-1) & 0x300) >> 4)
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#define LCD_HFPMSB(x) ((((x)-1) & 0x300) >> 8)
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#define LCD_INVMASK(x) ((x) & 0x3F00000)
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/* LCD Raster Ctrl Register */
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#define LCD_TFT_24BPP_MODE (1 << 25)
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#define LCD_TFT_24BPP_UNPACK (1 << 26)
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#define LCD_PALMODE_RAWDATA (0x02 << 20)
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#define LCD_TFT_MODE (0x01 << 7)
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#define LCD_RASTER_ENABLE (0x01 << 0)
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/* Macro definitions */
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#define FBSIZE(x) ((x->hactive * x->vactive * x->bpp) >> 3)
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struct am335x_lcdhw {
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unsigned int pid; /* 0x00 */
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unsigned int ctrl; /* 0x04 */
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unsigned int gap0; /* 0x08 */
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unsigned int lidd_ctrl; /* 0x0C */
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unsigned int lidd_cs0_conf; /* 0x10 */
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unsigned int lidd_cs0_addr; /* 0x14 */
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unsigned int lidd_cs0_data; /* 0x18 */
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unsigned int lidd_cs1_conf; /* 0x1C */
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unsigned int lidd_cs1_addr; /* 0x20 */
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unsigned int lidd_cs1_data; /* 0x24 */
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unsigned int raster_ctrl; /* 0x28 */
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unsigned int raster_timing0; /* 0x2C */
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unsigned int raster_timing1; /* 0x30 */
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unsigned int raster_timing2; /* 0x34 */
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unsigned int raster_subpanel; /* 0x38 */
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unsigned int raster_subpanel2; /* 0x3C */
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unsigned int lcddma_ctrl; /* 0x40 */
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unsigned int lcddma_fb0_base; /* 0x44 */
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unsigned int lcddma_fb0_ceiling; /* 0x48 */
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unsigned int lcddma_fb1_base; /* 0x4C */
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unsigned int lcddma_fb1_ceiling; /* 0x50 */
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unsigned int sysconfig; /* 0x54 */
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unsigned int irqstatus_raw; /* 0x58 */
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unsigned int irqstatus; /* 0x5C */
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unsigned int irqenable_set; /* 0x60 */
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unsigned int irqenable_clear; /* 0x64 */
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unsigned int gap1; /* 0x68 */
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unsigned int clkc_enable; /* 0x6C */
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unsigned int clkc_reset; /* 0x70 */
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};
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static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE;
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DECLARE_GLOBAL_DATA_PTR;
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int lcd_get_size(int *line_length)
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{
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*line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
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return *line_length * panel_info.vl_row + 0x20;
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}
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int am335xfb_init(struct am335x_lcdpanel *panel)
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{
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u32 raster_ctrl = 0;
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struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
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struct dpll_params dpll_disp = { 1, 0, 1, -1, -1, -1, -1 };
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unsigned int m, n, d, best_d = 2;
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int err = 0, err_r = 0;
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if (gd->fb_base == 0) {
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printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n");
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return -1;
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}
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if (panel == NULL) {
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printf("ERROR: missing ptr to am335x_lcdpanel!\n");
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return -1;
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}
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/* We can already set the bits for the raster_ctrl in this check */
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switch (panel->bpp) {
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case 16:
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break;
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case 32:
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raster_ctrl |= LCD_TFT_24BPP_UNPACK;
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/* fallthrough */
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case 24:
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raster_ctrl |= LCD_TFT_24BPP_MODE;
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break;
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default:
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pr_err("am335x-fb: invalid bpp value: %d\n", panel->bpp);
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return -1;
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}
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/* check given clock-frequency */
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if (panel->pxl_clk > (LCDC_FMAX / 2)) {
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pr_err("am335x-fb: requested pxl-clk: %d not supported!\n",
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panel->pxl_clk);
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return -1;
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}
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debug("setting up LCD-Controller for %dx%dx%d (hfp=%d,hbp=%d,hsw=%d / ",
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panel->hactive, panel->vactive, panel->bpp,
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panel->hfp, panel->hbp, panel->hsw);
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debug("vfp=%d,vbp=%d,vsw=%d / clk=%d)\n",
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panel->vfp, panel->vfp, panel->vsw, panel->pxl_clk);
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debug("using frambuffer at 0x%08x with size %d.\n",
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(unsigned int)gd->fb_base, FBSIZE(panel));
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/* setup display pll for requested clock frequency */
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err = panel->pxl_clk;
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err_r = err;
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for (d = 2; d < 255; d++) {
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for (m = 2; m < 2047; m++) {
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if ((V_OSCK * m) < (panel->pxl_clk * d))
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continue;
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n = (V_OSCK * m) / (panel->pxl_clk * d);
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if (n > 127)
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break;
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if (((V_OSCK * m) / n) > LCDC_FMAX)
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break;
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err = abs((V_OSCK * m) / n / d - panel->pxl_clk);
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if (err < err_r) {
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err_r = err;
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dpll_disp.m = m;
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dpll_disp.n = n;
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best_d = d;
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}
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}
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}
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debug("%s: PLL: best error %d Hz (M %d, N %d, DISP %d)\n",
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__func__, err_r, dpll_disp.m, dpll_disp.n, best_d);
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do_setup_dpll(&dpll_disp_regs, &dpll_disp);
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/* clock source for LCDC from dispPLL M2 */
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writel(0x0, &cmdpll->clklcdcpixelclk);
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/* palette default entry */
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memset((void *)gd->fb_base, 0, 0x20);
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*(unsigned int *)gd->fb_base = 0x4000;
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/* point fb behind palette */
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gd->fb_base += 0x20;
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/* turn ON display through powercontrol function if accessible */
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if (panel->panel_power_ctrl != NULL)
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panel->panel_power_ctrl(1);
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debug("am335x-fb: wait for stable power ...\n");
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mdelay(panel->pup_delay);
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lcdhw->clkc_enable = LCD_CORECLKEN | LCD_LIDDCLKEN | LCD_DMACLKEN;
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lcdhw->raster_ctrl = 0;
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lcdhw->ctrl = LCD_CLK_DIVISOR(best_d) | LCD_RASTER_MODE;
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lcdhw->lcddma_fb0_base = gd->fb_base;
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lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel);
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lcdhw->lcddma_fb1_base = gd->fb_base;
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lcdhw->lcddma_fb1_ceiling = gd->fb_base + FBSIZE(panel);
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lcdhw->lcddma_ctrl = LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
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lcdhw->raster_timing0 = LCD_HORLSB(panel->hactive) |
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LCD_HORMSB(panel->hactive) |
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LCD_HFPLSB(panel->hfp) |
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LCD_HBPLSB(panel->hbp) |
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LCD_HSWLSB(panel->hsw);
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lcdhw->raster_timing1 = LCD_VBP(panel->vbp) |
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LCD_VFP(panel->vfp) |
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LCD_VSW(panel->vsw) |
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LCD_VERLSB(panel->vactive);
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lcdhw->raster_timing2 = LCD_HSWMSB(panel->hsw) |
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LCD_VERMSB(panel->vactive) |
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LCD_INVMASK(panel->pol) |
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LCD_HBPMSB(panel->hbp) |
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LCD_HFPMSB(panel->hfp) |
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0x0000FF00; /* clk cycles for ac-bias */
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lcdhw->raster_ctrl = raster_ctrl |
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LCD_PALMODE_RAWDATA |
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LCD_TFT_MODE |
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LCD_RASTER_ENABLE;
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debug("am335x-fb: waiting picture to be stable.\n.");
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mdelay(panel->pon_delay);
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return 0;
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}
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