upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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259 lines
6.9 KiB
259 lines
6.9 KiB
/*
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* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <mach/ath79.h>
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#include <mach/ar71xx_regs.h>
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void _machine_restart(void)
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{
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void __iomem *base;
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u32 reg = 0;
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base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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if (soc_is_ar71xx())
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reg = AR71XX_RESET_REG_RESET_MODULE;
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else if (soc_is_ar724x())
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reg = AR724X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar913x())
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reg = AR913X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar933x())
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca953x())
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reg = QCA953X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca956x())
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reg = QCA956X_RESET_REG_RESET_MODULE;
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else
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puts("Reset register not defined for this SOC\n");
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if (reg)
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setbits_be32(base + reg, AR71XX_RESET_FULL_CHIP);
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while (1)
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/* NOP */;
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}
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u32 ath79_get_bootstrap(void)
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{
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void __iomem *base;
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u32 reg = 0;
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base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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if (soc_is_ar933x())
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reg = AR933X_RESET_REG_BOOTSTRAP;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_BOOTSTRAP;
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else if (soc_is_qca953x())
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reg = QCA953X_RESET_REG_BOOTSTRAP;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_BOOTSTRAP;
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else if (soc_is_qca956x())
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reg = QCA956X_RESET_REG_BOOTSTRAP;
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else
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puts("Bootstrap register not defined for this SOC\n");
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if (reg)
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return readl(base + reg);
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return 0;
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}
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static int eth_init_ar933x(void)
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{
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void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
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MAP_NOCACHE);
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void __iomem *gregs = map_physmem(AR933X_GMAC_BASE, AR933X_GMAC_SIZE,
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MAP_NOCACHE);
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const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO |
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AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO |
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AR933X_RESET_ETH_SWITCH |
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AR933X_RESET_ETH_SWITCH_ANALOG;
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/* Clear MDIO slave EN bit. */
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clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));
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mdelay(10);
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/* Get Atheros S26 PHY out of reset. */
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clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG,
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0x1f, 0x10);
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mdelay(10);
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setbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
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mdelay(10);
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clrbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask);
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mdelay(10);
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/* Configure AR93xx GMAC register. */
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clrsetbits_be32(gregs + AR933X_GMAC_REG_ETH_CFG,
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AR933X_ETH_CFG_MII_GE0_MASTER |
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AR933X_ETH_CFG_MII_GE0_SLAVE,
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AR933X_ETH_CFG_MII_GE0_SLAVE);
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return 0;
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}
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static int eth_init_ar934x(void)
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{
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void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
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MAP_NOCACHE);
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void __iomem *gregs = map_physmem(AR934X_GMAC_BASE, AR934X_GMAC_SIZE,
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MAP_NOCACHE);
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const u32 mask = AR934X_RESET_GE0_MAC | AR934X_RESET_GE0_MDIO |
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AR934X_RESET_GE1_MAC | AR934X_RESET_GE1_MDIO |
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AR934X_RESET_ETH_SWITCH_ANALOG;
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u32 reg;
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reg = readl(rregs + AR934X_RESET_REG_BOOTSTRAP);
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if (reg & AR934X_BOOTSTRAP_REF_CLK_40)
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writel(0x570, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
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else
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writel(0x271, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
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writel(BIT(26) | BIT(25), pregs + AR934X_PLL_ETH_XMII_CONTROL_REG);
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setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
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mdelay(1);
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clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
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mdelay(1);
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/* Configure AR934x GMAC register. */
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writel(AR934X_ETH_CFG_RGMII_GMAC0, gregs + AR934X_GMAC_REG_ETH_CFG);
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return 0;
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}
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static int eth_init_qca953x(void)
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{
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void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
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QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
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QCA953X_RESET_ETH_SWITCH_ANALOG |
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QCA953X_RESET_ETH_SWITCH;
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setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
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mdelay(1);
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clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
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mdelay(1);
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return 0;
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}
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int ath79_eth_reset(void)
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{
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/*
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* Un-reset ethernet. DM still doesn't have any notion of reset
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* framework, so we do it by hand here.
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*/
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if (soc_is_ar933x())
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return eth_init_ar933x();
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if (soc_is_ar934x())
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return eth_init_ar934x();
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if (soc_is_qca953x())
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return eth_init_qca953x();
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return -EINVAL;
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}
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static int usb_reset_ar933x(void __iomem *reset_regs)
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{
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/* Ungate the USB block */
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setbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
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AR933X_RESET_USBSUS_OVERRIDE);
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mdelay(1);
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clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
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AR933X_RESET_USB_HOST);
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mdelay(1);
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clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
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AR933X_RESET_USB_PHY);
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mdelay(1);
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return 0;
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}
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static int usb_reset_ar934x(void __iomem *reset_regs)
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{
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/* Ungate the USB block */
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setbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
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AR934X_RESET_USBSUS_OVERRIDE);
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mdelay(1);
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clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
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AR934X_RESET_USB_PHY);
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mdelay(1);
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clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
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AR934X_RESET_USB_PHY_ANALOG);
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mdelay(1);
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clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
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AR934X_RESET_USB_HOST);
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mdelay(1);
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return 0;
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}
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static int usb_reset_qca953x(void __iomem *reset_regs)
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{
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void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
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MAP_NOCACHE);
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clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
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0xf00, 0x200);
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mdelay(10);
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/* Ungate the USB block */
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setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
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QCA953X_RESET_USBSUS_OVERRIDE);
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mdelay(1);
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clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
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QCA953X_RESET_USB_PHY);
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mdelay(1);
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clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
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QCA953X_RESET_USB_PHY_ANALOG);
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mdelay(1);
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clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
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QCA953X_RESET_USB_HOST);
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mdelay(1);
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clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
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QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
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mdelay(1);
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return 0;
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}
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int ath79_usb_reset(void)
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{
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void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
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AR71XX_USB_CTRL_SIZE,
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MAP_NOCACHE);
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void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE,
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AR71XX_RESET_SIZE,
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MAP_NOCACHE);
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/*
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* Turn on the Buff and Desc swap bits.
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* NOTE: This write into an undocumented register in mandatory to
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* get the USB controller operational in BigEndian mode.
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*/
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writel(0xf0000, usbc_regs + AR71XX_USB_CTRL_REG_CONFIG);
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if (soc_is_ar933x())
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return usb_reset_ar933x(reset_regs);
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if (soc_is_ar934x())
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return usb_reset_ar934x(reset_regs);
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if (soc_is_qca953x())
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return usb_reset_qca953x(reset_regs);
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return -EINVAL;
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}
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