upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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84 lines
1.6 KiB
84 lines
1.6 KiB
/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/* Bus-to-Core Multipliers */
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static int bus2core[] = {
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3, 2, 2, 2, 4, 4, 5, 9,
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6, 11, 8, 10, 3, 12, 7, 0,
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6, 5, 13, 2, 14, 4, 15, 9,
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0, 11, 8, 10, 16, 12, 7, 0
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};
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/* ------------------------------------------------------------------------- */
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/*
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*
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*/
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int get_clocks (void)
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{
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ulong val, vco;
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#if !defined(CONFIG_SYS_MPC5XXX_CLKIN)
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#error clock measuring not implemented yet - define CONFIG_SYS_MPC5XXX_CLKIN
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#endif
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val = *(vu_long *)MPC5XXX_CDM_PORCFG;
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if (val & (1 << 6)) {
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vco = CONFIG_SYS_MPC5XXX_CLKIN * 12;
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} else {
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vco = CONFIG_SYS_MPC5XXX_CLKIN * 16;
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}
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if (val & (1 << 5)) {
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gd->bus_clk = vco / 8;
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} else {
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gd->bus_clk = vco / 4;
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}
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gd->cpu_clk = gd->bus_clk * bus2core[val & 0x1f] / 2;
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val = *(vu_long *)MPC5XXX_CDM_CFG;
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if (val & (1 << 8)) {
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gd->arch.ipb_clk = gd->bus_clk / 2;
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} else {
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gd->arch.ipb_clk = gd->bus_clk;
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}
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switch (val & 3) {
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case 0:
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gd->pci_clk = gd->arch.ipb_clk;
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break;
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case 1:
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gd->pci_clk = gd->arch.ipb_clk / 2;
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break;
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default:
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gd->pci_clk = gd->bus_clk / 4;
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break;
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}
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return (0);
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}
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int print_cpuinfo(void)
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{
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char buf1[32], buf2[32], buf3[32];
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printf (" Bus %s MHz, IPB %s MHz, PCI %s MHz\n",
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strmhz(buf1, gd->bus_clk),
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strmhz(buf2, gd->arch.ipb_clk),
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strmhz(buf3, gd->pci_clk)
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);
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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