upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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391 lines
11 KiB
391 lines
11 KiB
/*
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* Xilinx Zynq GPIO device driver
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*
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* Copyright (C) 2015 DAVE Embedded Systems <devel@dave.eu>
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*
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* Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
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* Copyright (C) 2009 - 2014 Xilinx, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <dm.h>
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#include <fdtdec.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Maximum banks */
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#define ZYNQ_GPIO_MAX_BANK 4
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#define ZYNQ_GPIO_BANK0_NGPIO 32
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#define ZYNQ_GPIO_BANK1_NGPIO 22
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#define ZYNQ_GPIO_BANK2_NGPIO 32
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#define ZYNQ_GPIO_BANK3_NGPIO 32
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#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
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ZYNQ_GPIO_BANK1_NGPIO + \
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ZYNQ_GPIO_BANK2_NGPIO + \
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ZYNQ_GPIO_BANK3_NGPIO)
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#define ZYNQMP_GPIO_MAX_BANK 6
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#define ZYNQMP_GPIO_BANK0_NGPIO 26
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#define ZYNQMP_GPIO_BANK1_NGPIO 26
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#define ZYNQMP_GPIO_BANK2_NGPIO 26
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#define ZYNQMP_GPIO_BANK3_NGPIO 32
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#define ZYNQMP_GPIO_BANK4_NGPIO 32
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#define ZYNQMP_GPIO_BANK5_NGPIO 32
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#define ZYNQMP_GPIO_NR_GPIOS 174
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#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
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#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
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ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
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#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
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#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
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ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
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#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
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#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
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ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
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#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
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#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
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ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
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#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
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#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
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ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
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#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
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#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
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ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
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/* Register offsets for the GPIO device */
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/* LSW Mask & Data -WO */
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#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
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/* MSW Mask & Data -WO */
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#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
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/* Data Register-RW */
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#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
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/* Direction mode reg-RW */
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#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
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/* Output enable reg-RW */
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#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
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/* Interrupt mask reg-RO */
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#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
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/* Interrupt enable reg-WO */
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#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
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/* Interrupt disable reg-WO */
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#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
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/* Interrupt status reg-RO */
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#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
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/* Interrupt type reg-RW */
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#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
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/* Interrupt polarity reg-RW */
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#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
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/* Interrupt on any, reg-RW */
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#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
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/* Disable all interrupts mask */
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#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
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/* Mid pin number of a bank */
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#define ZYNQ_GPIO_MID_PIN_NUM 16
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/* GPIO upper 16 bit mask */
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#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
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struct zynq_gpio_privdata {
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phys_addr_t base;
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const struct zynq_platform_data *p_data;
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};
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/**
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* struct zynq_platform_data - zynq gpio platform data structure
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* @label: string to store in gpio->label
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* @ngpio: max number of gpio pins
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* @max_bank: maximum number of gpio banks
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* @bank_min: this array represents bank's min pin
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* @bank_max: this array represents bank's max pin
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*/
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struct zynq_platform_data {
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const char *label;
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u16 ngpio;
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int max_bank;
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int bank_min[ZYNQMP_GPIO_MAX_BANK];
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int bank_max[ZYNQMP_GPIO_MAX_BANK];
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};
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static const struct zynq_platform_data zynqmp_gpio_def = {
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.label = "zynqmp_gpio",
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.ngpio = ZYNQMP_GPIO_NR_GPIOS,
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.max_bank = ZYNQMP_GPIO_MAX_BANK,
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.bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
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.bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
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.bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
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.bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
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.bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
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.bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
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.bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
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.bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
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.bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
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.bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
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.bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
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.bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
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};
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static const struct zynq_platform_data zynq_gpio_def = {
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.label = "zynq_gpio",
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.ngpio = ZYNQ_GPIO_NR_GPIOS,
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.max_bank = ZYNQ_GPIO_MAX_BANK,
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.bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
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.bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
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.bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
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.bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
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.bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
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.bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
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.bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
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.bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
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};
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/**
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* zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
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* for a given pin in the GPIO device
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* @pin_num: gpio pin number within the device
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* @bank_num: an output parameter used to return the bank number of the gpio
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* pin
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* @bank_pin_num: an output parameter used to return pin number within a bank
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* for the given gpio pin
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*
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* Returns the bank number and pin offset within the bank.
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*/
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static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
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unsigned int *bank_num,
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unsigned int *bank_pin_num,
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struct udevice *dev)
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{
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struct zynq_gpio_privdata *priv = dev_get_priv(dev);
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int bank;
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for (bank = 0; bank < priv->p_data->max_bank; bank++) {
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if ((pin_num >= priv->p_data->bank_min[bank]) &&
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(pin_num <= priv->p_data->bank_max[bank])) {
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*bank_num = bank;
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*bank_pin_num = pin_num -
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priv->p_data->bank_min[bank];
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return;
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}
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}
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if (bank >= priv->p_data->max_bank) {
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printf("Inavlid bank and pin num\n");
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*bank_num = 0;
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*bank_pin_num = 0;
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}
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}
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static int gpio_is_valid(unsigned gpio, struct udevice *dev)
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{
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struct zynq_gpio_privdata *priv = dev_get_priv(dev);
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return (gpio >= 0) && (gpio < priv->p_data->ngpio);
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}
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static int check_gpio(unsigned gpio, struct udevice *dev)
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{
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if (!gpio_is_valid(gpio, dev)) {
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printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
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return -1;
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}
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return 0;
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}
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static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio)
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{
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u32 data;
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unsigned int bank_num, bank_pin_num;
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struct zynq_gpio_privdata *priv = dev_get_priv(dev);
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if (check_gpio(gpio, dev) < 0)
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return -1;
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zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
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data = readl(priv->base +
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ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
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return (data >> bank_pin_num) & 1;
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}
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static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
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{
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unsigned int reg_offset, bank_num, bank_pin_num;
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struct zynq_gpio_privdata *priv = dev_get_priv(dev);
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if (check_gpio(gpio, dev) < 0)
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return -1;
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zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
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if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
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/* only 16 data bits in bit maskable reg */
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bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
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reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
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} else {
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reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
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}
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/*
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* get the 32 bit value to be written to the mask/data register where
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* the upper 16 bits is the mask and lower 16 bits is the data
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*/
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value = !!value;
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value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
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((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
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writel(value, priv->base + reg_offset);
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return 0;
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}
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static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio)
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{
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u32 reg;
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unsigned int bank_num, bank_pin_num;
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struct zynq_gpio_privdata *priv = dev_get_priv(dev);
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if (check_gpio(gpio, dev) < 0)
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return -1;
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zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
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/* bank 0 pins 7 and 8 are special and cannot be used as inputs */
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if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
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return -1;
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/* clear the bit in direction mode reg to set the pin as input */
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reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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reg &= ~BIT(bank_pin_num);
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writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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return 0;
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}
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static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio,
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int value)
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{
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u32 reg;
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unsigned int bank_num, bank_pin_num;
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struct zynq_gpio_privdata *priv = dev_get_priv(dev);
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if (check_gpio(gpio, dev) < 0)
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return -1;
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zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
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/* set the GPIO pin as output */
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reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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reg |= BIT(bank_pin_num);
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writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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/* configure the output enable reg for the pin */
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reg = readl(priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
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reg |= BIT(bank_pin_num);
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writel(reg, priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
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/* set the state of the pin */
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gpio_set_value(gpio, value);
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return 0;
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}
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static int zynq_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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u32 reg;
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unsigned int bank_num, bank_pin_num;
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struct zynq_gpio_privdata *priv = dev_get_priv(dev);
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if (check_gpio(offset, dev) < 0)
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return -1;
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zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev);
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/* set the GPIO pin as output */
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reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
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reg &= BIT(bank_pin_num);
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if (reg)
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return GPIOF_OUTPUT;
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else
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return GPIOF_INPUT;
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}
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static const struct dm_gpio_ops gpio_zynq_ops = {
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.direction_input = zynq_gpio_direction_input,
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.direction_output = zynq_gpio_direction_output,
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.get_value = zynq_gpio_get_value,
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.set_value = zynq_gpio_set_value,
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.get_function = zynq_gpio_get_function,
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};
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static const struct udevice_id zynq_gpio_ids[] = {
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{ .compatible = "xlnx,zynq-gpio-1.0",
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.data = (ulong)&zynq_gpio_def},
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{ .compatible = "xlnx,zynqmp-gpio-1.0",
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.data = (ulong)&zynqmp_gpio_def},
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{ }
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};
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static void zynq_gpio_getplat_data(struct udevice *dev)
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{
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const struct udevice_id *of_match = zynq_gpio_ids;
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int ret;
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struct zynq_gpio_privdata *priv = dev_get_priv(dev);
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while (of_match->compatible) {
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ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
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of_match->compatible);
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if (ret >= 0) {
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priv->p_data =
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(struct zynq_platform_data *)of_match->data;
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break;
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} else {
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of_match++;
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continue;
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}
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}
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if (!priv->p_data)
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printf("No Platform data found\n");
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}
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static int zynq_gpio_probe(struct udevice *dev)
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{
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struct zynq_gpio_privdata *priv = dev_get_priv(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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zynq_gpio_getplat_data(dev);
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if (priv->p_data)
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uc_priv->gpio_count = priv->p_data->ngpio;
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return 0;
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}
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static int zynq_gpio_ofdata_to_platdata(struct udevice *dev)
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{
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struct zynq_gpio_privdata *priv = dev_get_priv(dev);
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priv->base = dev_get_addr(dev);
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return 0;
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}
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U_BOOT_DRIVER(gpio_zynq) = {
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.name = "gpio_zynq",
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.id = UCLASS_GPIO,
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.ops = &gpio_zynq_ops,
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.of_match = zynq_gpio_ids,
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.ofdata_to_platdata = zynq_gpio_ofdata_to_platdata,
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.probe = zynq_gpio_probe,
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.priv_auto_alloc_size = sizeof(struct zynq_gpio_privdata),
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};
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