upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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407 lines
10 KiB
407 lines
10 KiB
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* Tegra2 clock control functions */
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#ifndef _CLOCK_H
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#define _CLOCK_H
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/* Set of oscillator frequencies supported in the internal API. */
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enum clock_osc_freq {
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/* All in MHz, so 13_0 is 13.0MHz */
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CLOCK_OSC_FREQ_13_0,
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CLOCK_OSC_FREQ_19_2,
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CLOCK_OSC_FREQ_12_0,
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CLOCK_OSC_FREQ_26_0,
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CLOCK_OSC_FREQ_COUNT,
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};
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/* The PLLs supported by the hardware */
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enum clock_id {
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CLOCK_ID_FIRST,
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CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
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CLOCK_ID_MEMORY,
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CLOCK_ID_PERIPH,
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CLOCK_ID_AUDIO,
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CLOCK_ID_USB,
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CLOCK_ID_DISPLAY,
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/* now the simple ones */
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CLOCK_ID_FIRST_SIMPLE,
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CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
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CLOCK_ID_EPCI,
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CLOCK_ID_SFROM32KHZ,
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/* These are the base clocks (inputs to the Tegra SOC) */
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CLOCK_ID_32KHZ,
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CLOCK_ID_OSC,
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CLOCK_ID_COUNT, /* number of clocks */
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CLOCK_ID_NONE = -1,
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};
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/* The clocks supported by the hardware */
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enum periph_id {
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PERIPH_ID_FIRST,
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/* Low word: 31:0 */
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PERIPH_ID_CPU = PERIPH_ID_FIRST,
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PERIPH_ID_RESERVED1,
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PERIPH_ID_RESERVED2,
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PERIPH_ID_AC97,
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PERIPH_ID_RTC,
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PERIPH_ID_TMR,
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PERIPH_ID_UART1,
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PERIPH_ID_UART2,
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/* 8 */
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PERIPH_ID_GPIO,
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PERIPH_ID_SDMMC2,
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PERIPH_ID_SPDIF,
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PERIPH_ID_I2S1,
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PERIPH_ID_I2C1,
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PERIPH_ID_NDFLASH,
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PERIPH_ID_SDMMC1,
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PERIPH_ID_SDMMC4,
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/* 16 */
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PERIPH_ID_TWC,
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PERIPH_ID_PWM,
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PERIPH_ID_I2S2,
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PERIPH_ID_EPP,
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PERIPH_ID_VI,
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PERIPH_ID_2D,
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PERIPH_ID_USBD,
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PERIPH_ID_ISP,
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/* 24 */
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PERIPH_ID_3D,
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PERIPH_ID_IDE,
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PERIPH_ID_DISP2,
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PERIPH_ID_DISP1,
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PERIPH_ID_HOST1X,
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PERIPH_ID_VCP,
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PERIPH_ID_RESERVED30,
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PERIPH_ID_CACHE2,
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/* Middle word: 63:32 */
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PERIPH_ID_MEM,
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PERIPH_ID_AHBDMA,
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PERIPH_ID_APBDMA,
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PERIPH_ID_RESERVED35,
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PERIPH_ID_KBC,
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PERIPH_ID_STAT_MON,
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PERIPH_ID_PMC,
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PERIPH_ID_FUSE,
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/* 40 */
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PERIPH_ID_KFUSE,
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PERIPH_ID_SBC1,
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PERIPH_ID_SNOR,
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PERIPH_ID_SPI1,
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PERIPH_ID_SBC2,
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PERIPH_ID_XIO,
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PERIPH_ID_SBC3,
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PERIPH_ID_DVC_I2C,
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/* 48 */
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PERIPH_ID_DSI,
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PERIPH_ID_TVO,
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PERIPH_ID_MIPI,
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PERIPH_ID_HDMI,
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PERIPH_ID_CSI,
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PERIPH_ID_TVDAC,
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PERIPH_ID_I2C2,
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PERIPH_ID_UART3,
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/* 56 */
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PERIPH_ID_RESERVED56,
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PERIPH_ID_EMC,
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PERIPH_ID_USB2,
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PERIPH_ID_USB3,
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PERIPH_ID_MPE,
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PERIPH_ID_VDE,
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PERIPH_ID_BSEA,
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PERIPH_ID_BSEV,
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/* Upper word 95:64 */
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PERIPH_ID_SPEEDO,
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PERIPH_ID_UART4,
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PERIPH_ID_UART5,
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PERIPH_ID_I2C3,
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PERIPH_ID_SBC4,
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PERIPH_ID_SDMMC3,
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PERIPH_ID_PCIE,
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PERIPH_ID_OWR,
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/* 72 */
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PERIPH_ID_AFI,
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PERIPH_ID_CORESIGHT,
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PERIPH_ID_RESERVED74,
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PERIPH_ID_AVPUCQ,
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PERIPH_ID_RESERVED76,
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PERIPH_ID_RESERVED77,
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PERIPH_ID_RESERVED78,
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PERIPH_ID_RESERVED79,
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/* 80 */
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PERIPH_ID_RESERVED80,
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PERIPH_ID_RESERVED81,
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PERIPH_ID_RESERVED82,
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PERIPH_ID_RESERVED83,
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PERIPH_ID_IRAMA,
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PERIPH_ID_IRAMB,
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PERIPH_ID_IRAMC,
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PERIPH_ID_IRAMD,
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/* 88 */
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PERIPH_ID_CRAM2,
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PERIPH_ID_COUNT,
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PERIPH_ID_NONE = -1,
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};
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/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
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#define PERIPH_REG(id) ((id) >> 5)
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/* Mask value for a clock (within PERIPH_REG(id)) */
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#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
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/* return 1 if a PLL ID is in range, and not a simple PLL */
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#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
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(id) < CLOCK_ID_FIRST_SIMPLE)
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/* PLL stabilization delay in usec */
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#define CLOCK_PLL_STABLE_DELAY_US 300
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/* return the current oscillator clock frequency */
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enum clock_osc_freq clock_get_osc_freq(void);
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/**
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* Start PLL using the provided configuration parameters.
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*
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* @param id clock id
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* @param divm input divider
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* @param divn feedback divider
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* @param divp post divider 2^n
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* @param cpcon charge pump setup control
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* @param lfcon loop filter setup control
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*
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* @returns monotonic time in us that the PLL will be stable
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*/
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unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
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u32 divp, u32 cpcon, u32 lfcon);
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/**
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* Read low-level parameters of a PLL.
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*
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* @param id clock id to read (note: USB is not supported)
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* @param divm returns input divider
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* @param divn returns feedback divider
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* @param divp returns post divider 2^n
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* @param cpcon returns charge pump setup control
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* @param lfcon returns loop filter setup control
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*
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* @returns 0 if ok, -1 on error (invalid clock id)
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*/
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int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
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u32 *divp, u32 *cpcon, u32 *lfcon);
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/*
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* Enable a clock
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*
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* @param id clock id
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*/
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void clock_enable(enum periph_id clkid);
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/*
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* Disable a clock
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*
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* @param id clock id
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*/
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void clock_disable(enum periph_id clkid);
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/*
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* Set whether a clock is enabled or disabled.
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*
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* @param id clock id
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* @param enable 1 to enable, 0 to disable
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*/
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void clock_set_enable(enum periph_id clkid, int enable);
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/**
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* Reset a peripheral. This puts it in reset, waits for a delay, then takes
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* it out of reset and waits for th delay again.
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*
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* @param periph_id peripheral to reset
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* @param us_delay time to delay in microseconds
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*/
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void reset_periph(enum periph_id periph_id, int us_delay);
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/**
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* Put a peripheral into or out of reset.
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*
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* @param periph_id peripheral to reset
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* @param enable 1 to put into reset, 0 to take out of reset
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*/
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void reset_set_enable(enum periph_id periph_id, int enable);
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/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
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enum crc_reset_id {
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/* Things we can hold in reset for each CPU */
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crc_rst_cpu = 1,
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crc_rst_de = 1 << 2, /* What is de? */
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crc_rst_watchdog = 1 << 3,
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crc_rst_debug = 1 << 4,
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};
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/**
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* Put parts of the CPU complex into or out of reset.\
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*
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* @param cpu cpu number (0 or 1 on Tegra2)
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* @param which which parts of the complex to affect (OR of crc_reset_id)
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* @param reset 1 to assert reset, 0 to de-assert
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*/
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void reset_cmplx_set_enable(int cpu, int which, int reset);
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/**
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* Set the source for a peripheral clock. This plus the divisor sets the
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* clock rate. You need to look up the datasheet to see the meaning of the
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* source parameter as it changes for each peripheral.
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*
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* Warning: This function is only for use pre-relocation. Please use
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* clock_start_periph_pll() instead.
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*
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* @param periph_id peripheral to adjust
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* @param source source clock (0, 1, 2 or 3)
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*/
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void clock_ll_set_source(enum periph_id periph_id, unsigned source);
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/**
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* Set the source and divisor for a peripheral clock. This sets the
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* clock rate. You need to look up the datasheet to see the meaning of the
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* source parameter as it changes for each peripheral.
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*
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* Warning: This function is only for use pre-relocation. Please use
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* clock_start_periph_pll() instead.
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*
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* @param periph_id peripheral to adjust
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* @param source source clock (0, 1, 2 or 3)
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* @param divisor divisor value to use
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*/
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void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
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unsigned divisor);
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/**
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* Start a peripheral PLL clock at the given rate. This also resets the
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* peripheral.
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*
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* @param periph_id peripheral to start
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* @param parent PLL id of required parent clock
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* @param rate Required clock rate in Hz
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* @return rate selected in Hz, or -1U if something went wrong
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*/
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unsigned clock_start_periph_pll(enum periph_id periph_id,
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enum clock_id parent, unsigned rate);
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/**
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* Returns the rate of a peripheral clock in Hz. Since the caller almost
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* certainly knows the parent clock (having just set it) we require that
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* this be passed in so we don't need to work it out.
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*
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* @param periph_id peripheral to start
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* @param parent PLL id of parent clock (used to calculate rate, you
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* must know this!)
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* @return clock rate of peripheral in Hz
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*/
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unsigned long clock_get_periph_rate(enum periph_id periph_id,
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enum clock_id parent);
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/**
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* Adjust peripheral PLL clock to the given rate. This does not reset the
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* peripheral. If a second stage divisor is not available, pass NULL for
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* extra_div. If it is available, then this parameter will return the
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* divisor selected (which will be a power of 2 from 1 to 256).
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*
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* @param periph_id peripheral to start
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* @param parent PLL id of required parent clock
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* @param rate Required clock rate in Hz
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* @param extra_div value for the second-stage divisor (NULL if one is
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not available)
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* @return rate selected in Hz, or -1U if something went wrong
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*/
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unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
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enum clock_id parent, unsigned rate, int *extra_div);
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/**
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* Returns the clock rate of a specified clock, in Hz.
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*
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* @param parent PLL id of clock to check
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* @return rate of clock in Hz
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*/
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unsigned clock_get_rate(enum clock_id clkid);
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/**
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* Start up a UART using low-level calls
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*
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* Prior to relocation clock_start_periph_pll() cannot be called. This
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* function provides a way to set up a UART using low-level calls which
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* do not require BSS.
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*
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* @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
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*/
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void clock_ll_start_uart(enum periph_id periph_id);
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/**
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* Decode a peripheral ID from a device tree node.
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*
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* This works by looking up the peripheral's 'clocks' node and reading out
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* the second cell, which is the clock number / peripheral ID.
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*
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* @param blob FDT blob to use
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* @param node Node to look at
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* @return peripheral ID, or PERIPH_ID_NONE if none
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*/
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enum periph_id clock_decode_periph_id(const void *blob, int node);
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/**
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* Checks if the oscillator bypass is enabled (XOBP bit)
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*
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* @return 1 if bypass is enabled, 0 if not
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*/
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int clock_get_osc_bypass(void);
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/*
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* Checks that clocks are valid and prints a warning if not
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*
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* @return 0 if ok, -1 on error
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*/
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int clock_verify(void);
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/* Initialize the clocks */
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void clock_init(void);
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/* Initialize the PLLs */
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void clock_early_init(void);
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#endif
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