upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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486 lines
13 KiB
486 lines
13 KiB
#
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# I2C subsystem configuration
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#
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menu "I2C support"
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config DM_I2C
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bool "Enable Driver Model for I2C drivers"
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depends on DM
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help
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Enable driver model for I2C. The I2C uclass interface: probe, read,
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write and speed, is implemented with the bus drivers operations,
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which provide methods for bus setting and data transfer. Each chip
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device (bus child) info is kept as parent platdata. The interface
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is defined in include/i2c.h. When i2c bus driver supports the i2c
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uclass, but the device drivers not, then DM_I2C_COMPAT config can
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be used as compatibility layer.
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config DM_I2C_COMPAT
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bool "Enable I2C compatibility layer"
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depends on DM
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help
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Enable old-style I2C functions for compatibility with existing code.
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This option can be enabled as a temporary measure to avoid needing
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to convert all code for a board in a single commit. It should not
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be enabled for any board in an official release.
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config I2C_CROS_EC_TUNNEL
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tristate "Chrome OS EC tunnel I2C bus"
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depends on CROS_EC
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help
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This provides an I2C bus that will tunnel i2c commands through to
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the other side of the Chrome OS EC to the I2C bus connected there.
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This will work whatever the interface used to talk to the EC (SPI,
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I2C or LPC). Some Chromebooks use this when the hardware design
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does not allow direct access to the main PMIC from the AP.
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config I2C_CROS_EC_LDO
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bool "Provide access to LDOs on the Chrome OS EC"
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depends on CROS_EC
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---help---
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On many Chromebooks the main PMIC is inaccessible to the AP. This is
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often dealt with by using an I2C pass-through interface provided by
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the EC. On some unfortunate models (e.g. Spring) the pass-through
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is not available, and an LDO message is available instead. This
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option enables a driver which provides very basic access to those
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regulators, via the EC. We implement this as an I2C bus which
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emulates just the TPS65090 messages we know about. This is done to
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avoid duplicating the logic in the TPS65090 regulator driver for
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enabling/disabling an LDO.
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config I2C_SET_DEFAULT_BUS_NUM
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bool "Set default I2C bus number"
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depends on DM_I2C
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help
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Set default number of I2C bus to be accessed. This option provides
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behaviour similar to old (i.e. pre DM) I2C bus driver.
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config I2C_DEFAULT_BUS_NUMBER
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hex "I2C default bus number"
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depends on I2C_SET_DEFAULT_BUS_NUM
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default 0x0
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help
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Number of default I2C bus to use
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config DM_I2C_GPIO
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bool "Enable Driver Model for software emulated I2C bus driver"
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depends on DM_I2C && DM_GPIO
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help
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Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
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configuration is given by the device tree. Kernel-style device tree
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bindings are supported.
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Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
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config SYS_I2C_AT91
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bool "Atmel I2C driver"
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depends on DM_I2C && ARCH_AT91
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help
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Add support for the Atmel I2C driver. A serious problem is that there
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is no documented way to issue repeated START conditions for more than
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two messages, as needed to support combined I2C messages. Use the
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i2c-gpio driver unless your system can cope with this limitation.
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Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
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config SYS_I2C_FSL
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bool "Freescale I2C bus driver"
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depends on DM_I2C
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help
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Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
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MPC85xx processors.
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config SYS_I2C_CADENCE
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tristate "Cadence I2C Controller"
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depends on DM_I2C && (ARCH_ZYNQ || ARM64)
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help
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Say yes here to select Cadence I2C Host Controller. This controller is
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e.g. used by Xilinx Zynq.
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config SYS_I2C_DAVINCI
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bool "Davinci I2C Controller"
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depends on (ARCH_KEYSTONE || ARCH_DAVINCI)
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help
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Say yes here to add support for Davinci and Keystone I2C controller
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config SYS_I2C_DW
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bool "Designware I2C Controller"
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default n
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help
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Say yes here to select the Designware I2C Host Controller. This
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controller is used in various SoCs, e.g. the ST SPEAr, Altera
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SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
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config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
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bool "DW I2C Enable Status Register not supported"
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depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
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TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
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default y
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help
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Some versions of the Designware I2C controller do not support the
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enable status register. This config option can be enabled in such
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cases.
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config SYS_I2C_ASPEED
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bool "Aspeed I2C Controller"
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depends on DM_I2C && ARCH_ASPEED
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help
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Say yes here to select Aspeed I2C Host Controller. The driver
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supports AST2500 and AST2400 controllers, but is very limited.
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Only single master mode is supported and only byte-by-byte
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synchronous reads and writes are supported, no Pool Buffers or DMA.
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config SYS_I2C_INTEL
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bool "Intel I2C/SMBUS driver"
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depends on DM_I2C
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help
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Add support for the Intel SMBUS driver. So far this driver is just
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a stub which perhaps some basic init. There is no implementation of
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the I2C API meaning that any I2C operations will immediately fail
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for now.
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config SYS_I2C_IMX_LPI2C
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bool "NXP i.MX LPI2C driver"
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help
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Add support for the NXP i.MX LPI2C driver.
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config SYS_I2C_MESON
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bool "Amlogic Meson I2C driver"
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depends on DM_I2C && ARCH_MESON
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help
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Add support for the I2C controller available in Amlogic Meson
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SoCs. The controller supports programmable bus speed including
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standard (100kbits/s) and fast (400kbit/s) speed and allows the
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software to define a flexible format of the bit streams. It has an
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internal buffer holding up to 8 bytes for transfers and supports
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both 7-bit and 10-bit addresses.
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config SYS_I2C_MXC
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bool "NXP MXC I2C driver"
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help
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Add support for the NXP I2C driver. This supports upto for bus
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channels and operating on standard mode upto 100 kbits/s and fast
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mode upto 400 kbits/s.
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if SYS_I2C_MXC
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config SYS_I2C_MXC_I2C1
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bool "NXP MXC I2C1"
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help
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Add support for NXP MXC I2C Controller 1.
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Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A
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config SYS_I2C_MXC_I2C2
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bool "NXP MXC I2C2"
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help
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Add support for NXP MXC I2C Controller 2.
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Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A
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config SYS_I2C_MXC_I2C3
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bool "NXP MXC I2C3"
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help
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Add support for NXP MXC I2C Controller 3.
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Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A
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config SYS_I2C_MXC_I2C4
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bool "NXP MXC I2C4"
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help
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Add support for NXP MXC I2C Controller 4.
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Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A
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config SYS_I2C_MXC_I2C5
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bool "NXP MXC I2C5"
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help
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Add support for NXP MXC I2C Controller 5.
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Required for SoCs which have I2C MXC controller 5 eg LX2160A
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config SYS_I2C_MXC_I2C6
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bool "NXP MXC I2C6"
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help
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Add support for NXP MXC I2C Controller 6.
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Required for SoCs which have I2C MXC controller 6 eg LX2160A
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config SYS_I2C_MXC_I2C7
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bool "NXP MXC I2C7"
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help
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Add support for NXP MXC I2C Controller 7.
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Required for SoCs which have I2C MXC controller 7 eg LX2160A
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config SYS_I2C_MXC_I2C8
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bool "NXP MXC I2C8"
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help
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Add support for NXP MXC I2C Controller 8.
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Required for SoCs which have I2C MXC controller 8 eg LX2160A
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endif
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if SYS_I2C_MXC_I2C1
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config SYS_MXC_I2C1_SPEED
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int "I2C Channel 1 speed"
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default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
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default 100000
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help
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MXC I2C Channel 1 speed
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config SYS_MXC_I2C1_SLAVE
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int "I2C1 Slave"
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default 0
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help
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MXC I2C1 Slave
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endif
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if SYS_I2C_MXC_I2C2
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config SYS_MXC_I2C2_SPEED
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int "I2C Channel 2 speed"
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default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
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default 100000
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help
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MXC I2C Channel 2 speed
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config SYS_MXC_I2C2_SLAVE
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int "I2C2 Slave"
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default 0
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help
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MXC I2C2 Slave
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endif
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if SYS_I2C_MXC_I2C3
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config SYS_MXC_I2C3_SPEED
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int "I2C Channel 3 speed"
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default 100000
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help
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MXC I2C Channel 3 speed
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config SYS_MXC_I2C3_SLAVE
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int "I2C3 Slave"
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default 0
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help
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MXC I2C3 Slave
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endif
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if SYS_I2C_MXC_I2C4
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config SYS_MXC_I2C4_SPEED
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int "I2C Channel 4 speed"
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default 100000
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help
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MXC I2C Channel 4 speed
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config SYS_MXC_I2C4_SLAVE
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int "I2C4 Slave"
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default 0
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help
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MXC I2C4 Slave
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endif
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if SYS_I2C_MXC_I2C5
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config SYS_MXC_I2C5_SPEED
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int "I2C Channel 5 speed"
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default 100000
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help
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MXC I2C Channel 5 speed
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config SYS_MXC_I2C5_SLAVE
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int "I2C5 Slave"
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default 0
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help
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MXC I2C5 Slave
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endif
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if SYS_I2C_MXC_I2C6
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config SYS_MXC_I2C6_SPEED
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int "I2C Channel 6 speed"
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default 100000
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help
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MXC I2C Channel 6 speed
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config SYS_MXC_I2C6_SLAVE
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int "I2C6 Slave"
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default 0
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help
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MXC I2C6 Slave
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endif
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if SYS_I2C_MXC_I2C7
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config SYS_MXC_I2C7_SPEED
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int "I2C Channel 7 speed"
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default 100000
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help
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MXC I2C Channel 7 speed
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config SYS_MXC_I2C7_SLAVE
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int "I2C7 Slave"
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default 0
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help
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MXC I2C7 Slave
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endif
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if SYS_I2C_MXC_I2C8
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config SYS_MXC_I2C8_SPEED
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int "I2C Channel 8 speed"
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default 100000
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help
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MXC I2C Channel 8 speed
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config SYS_MXC_I2C8_SLAVE
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int "I2C8 Slave"
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default 0
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help
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MXC I2C8 Slave
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endif
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config SYS_I2C_OMAP24XX
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bool "TI OMAP2+ I2C driver"
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depends on ARCH_OMAP2PLUS
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help
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Add support for the OMAP2+ I2C driver.
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if SYS_I2C_OMAP24XX
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config SYS_OMAP24_I2C_SLAVE
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int "I2C Slave addr channel 0"
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default 1
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help
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OMAP24xx I2C Slave address channel 0
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config SYS_OMAP24_I2C_SPEED
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int "I2C Slave channel 0 speed"
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default 100000
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help
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OMAP24xx Slave speed channel 0
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endif
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config SYS_I2C_RCAR_I2C
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bool "Renesas RCar I2C driver"
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depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
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help
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Support for Renesas RCar I2C controller.
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config SYS_I2C_RCAR_IIC
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bool "Renesas RCar Gen3 IIC driver"
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depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
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help
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Support for Renesas RCar Gen3 IIC controller.
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config SYS_I2C_ROCKCHIP
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bool "Rockchip I2C driver"
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depends on DM_I2C
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help
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Add support for the Rockchip I2C driver. This is used with various
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Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
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have several I2C ports and all are provided, controled by the
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device tree.
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config SYS_I2C_SANDBOX
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bool "Sandbox I2C driver"
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depends on SANDBOX && DM_I2C
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help
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Enable I2C support for sandbox. This is an emulation of a real I2C
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bus. Devices can be attached to the bus using the device tree
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which specifies the driver to use. See sandbox.dts as an example.
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config SYS_I2C_S3C24X0
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bool "Samsung I2C driver"
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depends on ARCH_EXYNOS4 && DM_I2C
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help
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Support for Samsung I2C controller as Samsung SoCs.
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config SYS_I2C_STM32F7
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bool "STMicroelectronics STM32F7 I2C support"
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depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
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help
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Enable this option to add support for STM32 I2C controller
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introduced with STM32F7/H7 SoCs. This I2C controller supports :
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_ Slave and master modes
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_ Multimaster capability
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_ Standard-mode (up to 100 kHz)
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_ Fast-mode (up to 400 kHz)
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_ Fast-mode Plus (up to 1 MHz)
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_ 7-bit and 10-bit addressing mode
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_ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
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_ All 7-bit addresses acknowledge mode
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_ General call
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_ Programmable setup and hold times
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_ Easy to use event management
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_ Optional clock stretching
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_ Software reset
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config SYS_I2C_UNIPHIER
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bool "UniPhier I2C driver"
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depends on ARCH_UNIPHIER && DM_I2C
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default y
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help
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Support for UniPhier I2C controller driver. This I2C controller
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is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
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config SYS_I2C_UNIPHIER_F
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bool "UniPhier FIFO-builtin I2C driver"
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depends on ARCH_UNIPHIER && DM_I2C
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default y
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help
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Support for UniPhier FIFO-builtin I2C controller driver.
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This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
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config SYS_I2C_MVTWSI
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bool "Marvell I2C driver"
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depends on DM_I2C
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help
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Support for Marvell I2C controllers as used on the orion5x and
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kirkwood SoC families.
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config TEGRA186_BPMP_I2C
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bool "Enable Tegra186 BPMP-based I2C driver"
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depends on TEGRA186_BPMP
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help
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Support for Tegra I2C controllers managed by the BPMP (Boot and
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Power Management Processor). On Tegra186, some I2C controllers are
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directly controlled by the main CPU, whereas others are controlled
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by the BPMP, and can only be accessed by the main CPU via IPC
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requests to the BPMP. This driver covers the latter case.
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config SYS_I2C_BUS_MAX
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int "Max I2C busses"
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depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
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default 2 if TI816X
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default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
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default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
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default 5 if OMAP54XX
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help
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Define the maximum number of available I2C buses.
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config SYS_I2C_ZYNQ
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bool "Xilinx I2C driver"
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depends on ARCH_ZYNQMP || ARCH_ZYNQ
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help
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Support for Xilinx I2C controller.
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config SYS_I2C_ZYNQ_SLAVE
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hex "Set slave addr"
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depends on SYS_I2C_ZYNQ
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default 0
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help
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Set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr.
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config SYS_I2C_ZYNQ_SPEED
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int "Set I2C speed"
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depends on SYS_I2C_ZYNQ
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default 100000
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help
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Set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting.
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config ZYNQ_I2C0
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bool "Xilinx I2C0 controller"
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depends on SYS_I2C_ZYNQ
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help
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Enable Xilinx I2C0 controller.
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config ZYNQ_I2C1
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bool "Xilinx I2C1 controller"
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depends on SYS_I2C_ZYNQ
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help
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Enable Xilinx I2C1 controller.
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config SYS_I2C_IHS
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bool "gdsys IHS I2C driver"
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depends on DM_I2C
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help
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Support for gdsys IHS I2C driver on FPGA bus.
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source "drivers/i2c/muxes/Kconfig"
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endmenu
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