upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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230 lines
9.9 KiB
230 lines
9.9 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*/
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#ifndef __DTSEC_H__
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#define __DTSEC_H__
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#include <asm/types.h>
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struct dtsec {
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u32 tsec_id; /* controller ID and version */
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u32 tsec_id2; /* controller ID and configuration */
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u32 ievent; /* interrupt event */
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u32 imask; /* interrupt mask */
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u32 res0;
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u32 ecntrl; /* ethernet control and configuration */
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u32 ptv; /* pause time value */
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u32 tbipa; /* TBI PHY address */
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u32 res1[8];
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u32 tctrl; /* Transmit control register */
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u32 res2[3];
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u32 rctrl; /* Receive control register */
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u32 res3[11];
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u32 igaddr[8]; /* Individual group address */
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u32 gaddr[8]; /* group address */
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u32 res4[16];
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u32 maccfg1; /* MAC configuration register 1 */
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u32 maccfg2; /* MAC configuration register 2 */
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u32 ipgifg; /* inter-packet/inter-frame gap */
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u32 hafdup; /* half-duplex control */
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u32 maxfrm; /* Maximum frame size */
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u32 res5[3];
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u32 miimcfg; /* MII management configuration */
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u32 miimcom; /* MII management command */
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u32 miimadd; /* MII management address */
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u32 miimcon; /* MII management control */
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u32 miimstat; /* MII management status */
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u32 miimind; /* MII management indicator */
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u32 res6;
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u32 ifstat; /* Interface status */
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u32 macstnaddr1; /* MAC station address 1 */
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u32 macstnaddr2; /* MAC station address 2 */
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u32 res7[46];
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/* transmit and receive counter */
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u32 tr64; /* Tx and Rx 64 bytes frame */
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u32 tr127; /* Tx and Rx 65 to 127 bytes frame */
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u32 tr255; /* Tx and Rx 128 to 255 bytes frame */
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u32 tr511; /* Tx and Rx 256 to 511 bytes frame */
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u32 tr1k; /* Tx and Rx 512 to 1023 bytes frame */
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u32 trmax; /* Tx and Rx 1024 to 1518 bytes frame */
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u32 trmgv; /* Tx and Rx 1519 to 1522 good VLAN frame */
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/* receive counters */
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u32 rbyt; /* Receive byte counter */
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u32 rpkt; /* Receive packet counter */
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u32 rfcs; /* Receive FCS error */
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u32 rmca; /* Receive multicast packet */
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u32 rbca; /* Receive broadcast packet */
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u32 rxcf; /* Receive control frame */
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u32 rxpf; /* Receive pause frame */
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u32 rxuo; /* Receive unknown OP code */
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u32 raln; /* Receive alignment error */
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u32 rflr; /* Receive frame length error */
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u32 rcde; /* Receive code error */
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u32 rcse; /* Receive carrier sense error */
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u32 rund; /* Receive undersize packet */
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u32 rovr; /* Receive oversize packet */
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u32 rfrg; /* Receive fragments counter */
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u32 rjbr; /* Receive jabber counter */
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u32 rdrp; /* Receive drop counter */
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/* transmit counters */
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u32 tbyt; /* Transmit byte counter */
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u32 tpkt; /* Transmit packet */
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u32 tmca; /* Transmit multicast packet */
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u32 tbca; /* Transmit broadcast packet */
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u32 txpf; /* Transmit pause control frame */
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u32 tdfr; /* Transmit deferral packet */
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u32 tedf; /* Transmit excessive deferral pkt */
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u32 tscl; /* Transmit single collision pkt */
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u32 tmcl; /* Transmit multiple collision pkt */
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u32 tlcl; /* Transmit late collision pkt */
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u32 txcl; /* Transmit excessive collision */
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u32 tncl; /* Transmit total collision */
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u32 res8;
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u32 tdrp; /* Transmit drop frame */
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u32 tjbr; /* Transmit jabber frame */
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u32 tfcs; /* Transmit FCS error */
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u32 txcf; /* Transmit control frame */
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u32 tovr; /* Transmit oversize frame */
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u32 tund; /* Transmit undersize frame */
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u32 tfrg; /* Transmit fragments frame */
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/* counter controls */
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u32 car1; /* carry register 1 */
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u32 car2; /* carry register 2 */
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u32 cam1; /* carry register 1 mask */
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u32 cam2; /* carry register 2 mask */
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u32 res9[80];
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};
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/* TBI register addresses */
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#define TBI_CR 0x00
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#define TBI_SR 0x01
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#define TBI_ANA 0x04
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#define TBI_ANLPBPA 0x05
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#define TBI_ANEX 0x06
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#define TBI_TBICON 0x11
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/* TBI MDIO register bit fields*/
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#define TBICON_CLK_SELECT 0x0020
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#define TBIANA_ASYMMETRIC_PAUSE 0x0100
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#define TBIANA_SYMMETRIC_PAUSE 0x0080
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#define TBIANA_HALF_DUPLEX 0x0040
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#define TBIANA_FULL_DUPLEX 0x0020
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#define TBICR_PHY_RESET 0x8000
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#define TBICR_ANEG_ENABLE 0x1000
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#define TBICR_RESTART_ANEG 0x0200
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#define TBICR_FULL_DUPLEX 0x0100
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#define TBICR_SPEED1_SET 0x0040
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/* IEVENT - interrupt events register */
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#define IEVENT_BABR 0x80000000 /* Babbling receive error */
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#define IEVENT_RXC 0x40000000 /* pause control frame received */
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#define IEVENT_MSRO 0x04000000 /* MIB counter overflow */
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#define IEVENT_GTSC 0x02000000 /* Graceful transmit stop complete */
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#define IEVENT_BABT 0x01000000 /* Babbling transmit error */
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#define IEVENT_TXC 0x00800000 /* control frame transmitted */
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#define IEVENT_TXE 0x00400000 /* Transmit channel error */
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#define IEVENT_LC 0x00040000 /* Late collision occurred */
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#define IEVENT_CRL 0x00020000 /* Collision retry exceed limit */
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#define IEVENT_XFUN 0x00010000 /* Transmit FIFO underrun */
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#define IEVENT_ABRT 0x00008000 /* Transmit packet abort */
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#define IEVENT_MMRD 0x00000400 /* MII management read complete */
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#define IEVENT_MMWR 0x00000200 /* MII management write complete */
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#define IEVENT_GRSC 0x00000100 /* Graceful stop complete */
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#define IEVENT_TDPE 0x00000002 /* Internal data parity error on Tx */
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#define IEVENT_RDPE 0x00000001 /* Internal data parity error on Rx */
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#define IEVENT_CLEAR_ALL 0xffffffff
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/* IMASK - interrupt mask register */
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#define IMASK_BREN 0x80000000 /* Babbling receive enable */
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#define IMASK_RXCEN 0x40000000 /* receive control enable */
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#define IMASK_MSROEN 0x04000000 /* MIB counter overflow enable */
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#define IMASK_GTSCEN 0x02000000 /* Graceful Tx stop complete enable */
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#define IMASK_BTEN 0x01000000 /* Babbling transmit error enable */
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#define IMASK_TXCEN 0x00800000 /* control frame transmitted enable */
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#define IMASK_TXEEN 0x00400000 /* Transmit channel error enable */
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#define IMASK_LCEN 0x00040000 /* Late collision interrupt enable */
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#define IMASK_CRLEN 0x00020000 /* Collision retry exceed limit */
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#define IMASK_XFUNEN 0x00010000 /* Transmit FIFO underrun enable */
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#define IMASK_ABRTEN 0x00008000 /* Transmit packet abort enable */
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#define IMASK_MMRDEN 0x00000400 /* MII management read complete enable */
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#define IMASK_MMWREN 0x00000200 /* MII management write complete enable */
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#define IMASK_GRSCEN 0x00000100 /* Graceful stop complete interrupt enable */
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#define IMASK_TDPEEN 0x00000002 /* Internal data parity error on Tx enable */
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#define IMASK_RDPEEN 0x00000001 /* Internal data parity error on Rx enable */
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#define IMASK_MASK_ALL 0x00000000
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/* ECNTRL - ethernet control register */
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#define ECNTRL_CFG_RO 0x80000000 /* GMIIM, RPM, R100M, SGMIIM bits are RO */
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#define ECNTRL_CLRCNT 0x00004000 /* clear all statistics */
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#define ECNTRL_AUTOZ 0x00002000 /* auto zero MIB counter */
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#define ECNTRL_STEN 0x00001000 /* enable internal counters to update */
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#define ECNTRL_GMIIM 0x00000040 /* 1- GMII or RGMII interface mode */
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#define ECNTRL_TBIM 0x00000020 /* 1- Ten-bit interface mode */
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#define ECNTRL_RPM 0x00000010 /* 1- RGMII reduced-pin mode */
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#define ECNTRL_R100M 0x00000008 /* 1- RGMII 100 Mbps, SGMII 100 Mbps
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0- RGMII 10 Mbps, SGMII 10 Mbps */
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#define ECNTRL_SGMIIM 0x00000002 /* 1- SGMII interface mode */
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#define ECNTRL_TBIM 0x00000020 /* 1- TBI Interface mode (for SGMII) */
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#define ECNTRL_DEFAULT (ECNTRL_TBIM | ECNTRL_R100M | ECNTRL_SGMIIM)
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/* TCTRL - Transmit control register */
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#define TCTRL_THDF 0x00000800 /* Transmit half-duplex flow control */
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#define TCTRL_TTSE 0x00000040 /* Transmit time-stamp enable */
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#define TCTRL_GTS 0x00000020 /* Graceful transmit stop */
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#define TCTRL_RFC_PAUSE 0x00000010 /* Receive flow control pause frame */
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/* RCTRL - Receive control register */
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#define RCTRL_PAL_MASK 0x001f0000 /* packet alignment padding length */
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#define RCTRL_PAL_SHIFT 16
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#define RCTRL_CFA 0x00008000 /* control frame accept enable */
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#define RCTRL_GHTX 0x00000800 /* group address hash table extend */
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#define RCTRL_RTSE 0x00000040 /* receive 1588 time-stamp enable */
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#define RCTRL_GRS 0x00000020 /* graceful receive stop */
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#define RCTRL_BC_REJ 0x00000010 /* broadcast frame reject */
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#define RCTRL_BC_MPROM 0x00000008 /* all multicast/broadcast frames received */
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#define RCTRL_RSF 0x00000004 /* receive short frame(17~63 bytes) enable */
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#define RCTRL_EMEN 0x00000002 /* Exact match MAC address enable */
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#define RCTRL_UPROM 0x00000001 /* all unicast frame received */
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/* MACCFG1 - MAC configuration 1 register */
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#define MACCFG1_SOFT_RST 0x80000000 /* place the MAC in reset */
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#define MACCFG1_RST_RXMAC 0x00080000 /* reset receive MAC control block */
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#define MACCFG1_RST_TXMAC 0x00040000 /* reet transmit MAC control block */
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#define MACCFG1_RST_RXFUN 0x00020000 /* reset receive function block */
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#define MACCFG1_RST_TXFUN 0x00010000 /* reset transmit function block */
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#define MACCFG1_LOOPBACK 0x00000100 /* MAC loopback */
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#define MACCFG1_RX_FLOW 0x00000020 /* Receive flow */
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#define MACCFG1_TX_FLOW 0x00000010 /* Transmit flow */
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#define MACCFG1_SYNC_RXEN 0x00000008 /* Frame reception enabled */
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#define MACCFG1_RX_EN 0x00000004 /* Rx enable */
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#define MACCFG1_SYNC_TXEN 0x00000002 /* Frame transmission is enabled */
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#define MACCFG1_TX_EN 0x00000001 /* Tx enable */
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#define MACCFG1_RXTX_EN (MACCFG1_RX_EN | MACCFG1_TX_EN)
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/* MACCFG2 - MAC configuration 2 register */
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#define MACCFG2_PRE_LEN_MASK 0x0000f000 /* preamble length */
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#define MACCFG2_PRE_LEN(x) ((x << 12) & MACCFG2_PRE_LEN_MASK)
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#define MACCFG2_IF_MODE_MASK 0x00000300
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#define MACCFG2_IF_MODE_NIBBLE 0x00000100 /* MII, 10/100 Mbps MII/RMII */
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#define MACCFG2_IF_MODE_BYTE 0x00000200 /* GMII/TBI, 1000 GMII/TBI */
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#define MACCFG2_PRE_RX_EN 0x00000080 /* receive preamble enable */
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#define MACCFG2_PRE_TX_EN 0x00000040 /* tx preable enable */
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#define MACCFG2_HUGE_FRAME 0x00000020 /* >= max frame len enable */
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#define MACCFG2_LEN_CHECK 0x00000010 /* MAC check frame's length Rx */
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#define MACCFG2_MAG_EN 0x00000008 /* magic packet enable */
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#define MACCFG2_PAD_CRC 0x00000004 /* pad and append CRC */
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#define MACCFG2_CRC_EN 0x00000002 /* MAC appends a CRC on all frames */
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#define MACCFG2_FULL_DUPLEX 0x00000001 /* Full deplex mode */
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struct fsl_enet_mac;
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void init_dtsec(struct fsl_enet_mac *mac, void *base, void *phyregs,
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int max_rx_len);
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#endif
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