upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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111 lines
3.4 KiB
111 lines
3.4 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2012 Samsung Electronics
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* R. Chandrasekar <rcsekar@samsung.com>
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*/
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#ifndef __I2S_H__
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#define __I2S_H__
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/*
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* DAI hardware audio formats.
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*
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* Describes the physical PCM data formating and clocking. Add new formats
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* to the end.
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*/
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#define SND_SOC_DAIFMT_I2S 1 /* I2S mode */
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#define SND_SOC_DAIFMT_RIGHT_J 2 /* Right Justified mode */
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#define SND_SOC_DAIFMT_LEFT_J 3 /* Left Justified mode */
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#define SND_SOC_DAIFMT_DSP_A 4 /* L data MSB after FRM LRC */
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#define SND_SOC_DAIFMT_DSP_B 5 /* L data MSB during FRM LRC */
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#define SND_SOC_DAIFMT_AC97 6 /* AC97 */
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#define SND_SOC_DAIFMT_PDM 7 /* Pulse density modulation */
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/* left and right justified also known as MSB and LSB respectively */
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#define SND_SOC_DAIFMT_MSB SND_SOC_DAIFMT_LEFT_J
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#define SND_SOC_DAIFMT_LSB SND_SOC_DAIFMT_RIGHT_J
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/*
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* DAI hardware signal inversions.
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*
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* Specifies whether the DAI can also support inverted clocks for the specified
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* format.
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*/
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#define SND_SOC_DAIFMT_NB_NF (1 << 8) /* normal bit clock + frame */
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#define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */
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#define SND_SOC_DAIFMT_IB_NF (3 << 8) /* invert BCLK + nor FRM */
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#define SND_SOC_DAIFMT_IB_IF (4 << 8) /* invert BCLK + FRM */
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/*
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* DAI hardware clock masters.
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*
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* This is wrt the codec, the inverse is true for the interface
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* i.e. if the codec is clk and FRM master then the interface is
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* clk and frame slave.
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*/
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#define SND_SOC_DAIFMT_CBM_CFM (1 << 12) /* codec clk & FRM master */
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#define SND_SOC_DAIFMT_CBS_CFM (2 << 12) /* codec clk slave & FRM master */
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#define SND_SOC_DAIFMT_CBM_CFS (3 << 12) /* codec clk master & frame slave */
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#define SND_SOC_DAIFMT_CBS_CFS (4 << 12) /* codec clk & FRM slave */
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#define SND_SOC_DAIFMT_FORMAT_MASK 0x000f
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#define SND_SOC_DAIFMT_CLOCK_MASK 0x00f0
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#define SND_SOC_DAIFMT_INV_MASK 0x0f00
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#define SND_SOC_DAIFMT_MASTER_MASK 0xf000
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/*
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* Master Clock Directions
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*/
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#define SND_SOC_CLOCK_IN 0
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#define SND_SOC_CLOCK_OUT 1
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/* I2S Tx Control */
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#define I2S_TX_ON 1
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#define I2S_TX_OFF 0
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#define FIFO_LENGTH 64
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/* I2s Registers */
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struct i2s_reg {
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unsigned int con; /* base + 0 , Control register */
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unsigned int mod; /* Mode register */
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unsigned int fic; /* FIFO control register */
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unsigned int psr; /* Reserved */
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unsigned int txd; /* Transmit data register */
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unsigned int rxd; /* Receive Data Register */
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};
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/* This structure stores the i2s related information */
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struct i2stx_info {
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unsigned int rfs; /* LR clock frame size */
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unsigned int bfs; /* Bit slock frame size */
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unsigned int audio_pll_clk; /* Audio pll frequency in Hz */
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unsigned int samplingrate; /* sampling rate */
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unsigned int bitspersample; /* bits per sample */
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unsigned int channels; /* audio channels */
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unsigned int base_address; /* I2S Register Base */
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unsigned int id; /* I2S controller id */
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};
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/*
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* Sends the given data through i2s tx
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*
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* @param pi2s_tx pointer of i2s transmitter parameter structure.
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* @param data address of the data buffer
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* @param data_size array size of the int buffer (total size / size of int)
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*
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* @return int value 0 for success, -1 in case of error
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*/
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int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned *data,
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unsigned long data_size);
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/*
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* Initialise i2s transmiter
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*
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* @param pi2s_tx pointer of i2s transmitter parameter structure.
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*
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* @return int value 0 for success, -1 in case of error
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*/
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int i2s_tx_init(struct i2stx_info *pi2s_tx);
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#endif /* __I2S_H__ */
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