upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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83 lines
2.7 KiB
83 lines
2.7 KiB
/*
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#ifndef FSL_DDR_MAIN_H
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#define FSL_DDR_MAIN_H
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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#include "common_timing_params.h"
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/*
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* Bind the main DDR setup driver's generic names
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* to this specific DDR technology.
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*/
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static __inline__ int
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compute_dimm_parameters(const generic_spd_eeprom_t *spd,
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dimm_params_t *pdimm,
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unsigned int dimm_number)
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{
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return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
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}
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/*
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* Data Structures
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*
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* All data structures have to be on the stack
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*/
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#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
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#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
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typedef struct {
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generic_spd_eeprom_t
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spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
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struct dimm_params_s
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dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
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memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
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common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
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fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
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} fsl_ddr_info_t;
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/* Compute steps */
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#define STEP_GET_SPD (1 << 0)
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#define STEP_COMPUTE_DIMM_PARMS (1 << 1)
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#define STEP_COMPUTE_COMMON_PARMS (1 << 2)
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#define STEP_GATHER_OPTS (1 << 3)
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#define STEP_ASSIGN_ADDRESSES (1 << 4)
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#define STEP_COMPUTE_REGS (1 << 5)
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#define STEP_PROGRAM_REGS (1 << 6)
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#define STEP_ALL 0xFFF
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extern unsigned long long
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fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
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unsigned int size_only);
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extern const char * step_to_string(unsigned int step);
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extern unsigned int
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compute_fsl_memctl_config_regs(const memctl_options_t *popts,
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fsl_ddr_cfg_regs_t *ddr,
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const common_timing_params_t *common_dimm,
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const dimm_params_t *dimm_parameters,
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unsigned int dbw_capacity_adjust,
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unsigned int size_only);
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extern unsigned int
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compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
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common_timing_params_t *outpdimm,
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unsigned int number_of_dimms);
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extern unsigned int populate_memctl_options(int all_DIMMs_registered,
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memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num);
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extern void check_interleaving_options(fsl_ddr_info_t *pinfo);
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extern unsigned int mclk_to_picos(unsigned int mclk);
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extern unsigned int get_memory_clk_period_ps(void);
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extern unsigned int picos_to_mclk(unsigned int picos);
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#endif
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