upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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677 lines
16 KiB
677 lines
16 KiB
/*
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* -- Version 1.1 --
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*
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* (C) Copyright 2004-2005
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* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
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*
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* (C) Copyright 2006
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* Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
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*
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* History:
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* 1.1 - improved SM501 init to meet spec timing
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <pci.h>
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#ifdef CONFIG_VIDEO_SM501
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#include <sm501.h>
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#endif
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#if defined(CONFIG_MPC5200_DDR)
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#include "mt46v16m16-75.h"
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#else
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#include "mt48lc16m16a2-75.h"
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#endif
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#ifdef CONFIG_RTC_MPC5200
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#include <rtc.h>
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#endif
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#ifdef CONFIG_PS2MULT
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void ps2mult_early_init(void);
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#endif
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#ifndef CFG_RAMBOOT
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static void sdram_start (int hi_addr)
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{
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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/* unlock mode register */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
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hi_addr_bit;
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__asm__ volatile ("sync");
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
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hi_addr_bit;
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set mode register: extended mode */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
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__asm__ volatile ("sync");
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/* set mode register: reset DLL */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
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__asm__ volatile ("sync");
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#endif
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/* precharge all banks */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
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hi_addr_bit;
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__asm__ volatile ("sync");
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/* auto refresh */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
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hi_addr_bit;
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__asm__ volatile ("sync");
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/* set mode register */
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*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
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__asm__ volatile ("sync");
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/* normal operation */
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
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__asm__ volatile ("sync");
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}
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#endif
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/*
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* ATTENTION: Although partially referenced initdram does NOT make real use
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* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
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* is something else than 0x00000000.
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*/
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#if defined(CONFIG_MPC5200)
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long int initdram (int board_type)
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{
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ulong dramsize = 0;
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ulong dramsize2 = 0;
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#ifndef CFG_RAMBOOT
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ulong test1, test2;
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/* setup SDRAM chip selects */
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
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__asm__ volatile ("sync");
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/* setup config registers */
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*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
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*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set tap delay */
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*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
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__asm__ volatile ("sync");
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#endif
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/* find RAM size using SDRAM CS0 only */
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sdram_start(0);
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test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
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sdram_start(1);
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test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20)) {
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dramsize = 0;
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}
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/* set SDRAM CS0 size according to the amount of RAM found */
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if (dramsize > 0) {
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
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__builtin_ffs(dramsize >> 20) - 1;
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} else {
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*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
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}
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/* let SDRAM CS1 start right after CS0 */
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
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/* find RAM size using SDRAM CS1 only */
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sdram_start(0);
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test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
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sdram_start(1);
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test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize2 = test1;
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} else {
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dramsize2 = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize2 < (1 << 20)) {
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dramsize2 = 0;
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}
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/* set SDRAM CS1 size according to the amount of RAM found */
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if (dramsize2 > 0) {
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
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| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
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} else {
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*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
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}
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#else /* CFG_RAMBOOT */
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/* retrieve size of memory connected to SDRAM CS0 */
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dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
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if (dramsize >= 0x13) {
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dramsize = (1 << (dramsize - 0x13)) << 20;
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} else {
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dramsize = 0;
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}
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/* retrieve size of memory connected to SDRAM CS1 */
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dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
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if (dramsize2 >= 0x13) {
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dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
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} else {
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dramsize2 = 0;
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}
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#endif /* CFG_RAMBOOT */
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return dramsize;
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}
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#elif defined(CONFIG_MGT5100)
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long int initdram (int board_type)
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{
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ulong dramsize = 0;
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#ifndef CFG_RAMBOOT
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ulong test1, test2;
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/* setup and enable SDRAM chip selects */
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*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
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*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff; /* 2G */
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*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
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__asm__ volatile ("sync");
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/* setup config registers */
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*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
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*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
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/* address select register */
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*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
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__asm__ volatile ("sync");
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/* find RAM size */
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sdram_start(0);
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test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
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sdram_start(1);
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test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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/* set SDRAM end address according to size */
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*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
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#else /* CFG_RAMBOOT */
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/* Retrieve amount of SDRAM available */
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dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
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#endif /* CFG_RAMBOOT */
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return dramsize;
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}
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#else
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#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
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#endif
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int checkboard (void)
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{
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#if defined (CONFIG_TQM5200)
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puts ("Board: TQM5200 (TQ-Components GmbH)\n");
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#endif
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#if defined (CONFIG_BC3450)
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puts ("Dev: GERSYS BC3450\n");
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#endif
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return 0;
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}
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void flash_preinit(void)
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{
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/*
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* Now, when we are in RAM, enable flash write
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* access for detection process.
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* Note that CS_BOOT cannot be cleared when
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* executing in flash.
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*/
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#if defined(CONFIG_MGT5100)
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*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
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*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
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#endif
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*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
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}
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#ifdef CONFIG_PCI
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static struct pci_controller hose;
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extern void pci_mpc5xxx_init(struct pci_controller *);
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void pci_init_board(void)
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{
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pci_mpc5xxx_init(&hose);
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}
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#endif
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#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
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#define GPIO_PSC1_4 0x01000000UL
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void init_ide_reset (void)
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{
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debug ("init_ide_reset\n");
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/* Configure PSC1_4 as GPIO output for ATA reset */
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*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
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*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
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}
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void ide_set_reset (int idereset)
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{
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debug ("ide_reset(%d)\n", idereset);
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if (idereset) {
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*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
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} else {
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*(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
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}
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}
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#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
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#ifdef CONFIG_POST
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/*
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* Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
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* is left open, no keypress is detected.
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*/
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int post_hotkeys_pressed(void)
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{
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struct mpc5xxx_gpio *gpio;
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gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
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/*
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* Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
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* CODEC or UART mode. Consumer IrDA should still be possible.
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*/
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gpio->port_config &= ~(0x07000000);
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gpio->port_config |= 0x03000000;
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/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
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gpio->simple_gpioe |= 0x20000000;
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/* Configure GPIO_IRDA_1 as input */
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gpio->simple_ddr &= ~(0x20000000);
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return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
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}
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#endif
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#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
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void post_word_store (ulong a)
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{
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volatile ulong *save_addr =
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(volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
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*save_addr = a;
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}
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ulong post_word_load (void)
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{
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volatile ulong *save_addr =
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(volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
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return *save_addr;
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}
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#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
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#ifdef CONFIG_BOARD_EARLY_INIT_R
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int board_early_init_r (void)
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{
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#ifdef CONFIG_RTC_MPC5200
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struct rtc_time t;
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/* set to Wed Dec 31 19:00:00 1969 */
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t.tm_sec = t.tm_min = 0;
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t.tm_hour = 19;
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t.tm_mday = 31;
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t.tm_mon = 12;
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t.tm_year = 1969;
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t.tm_wday = 3;
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rtc_set(&t);
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#endif /* CONFIG_RTC_MPC5200 */
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#ifdef CONFIG_PS2MULT
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ps2mult_early_init();
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#endif /* CONFIG_PS2MULT */
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return (0);
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}
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#endif /* CONFIG_BOARD_EARLY_INIT_R */
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int last_stage_init (void)
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{
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/*
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* auto scan for really existing devices and re-set chip select
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* configuration.
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*/
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u16 save, tmp;
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int restore;
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/*
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* Check for SRAM and SRAM size
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*/
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/* save original SRAM content */
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save = *(volatile u16 *)CFG_CS2_START;
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restore = 1;
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/* write test pattern to SRAM */
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*(volatile u16 *)CFG_CS2_START = 0xA5A5;
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__asm__ volatile ("sync");
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/*
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* Put a different pattern on the data lines: otherwise they may float
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* long enough to read back what we wrote.
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*/
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tmp = *(volatile u16 *)CFG_FLASH_BASE;
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if (tmp == 0xA5A5)
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puts ("!! possible error in SRAM detection\n");
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if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
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/* no SRAM at all, disable cs */
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*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
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*(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
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*(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
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restore = 0;
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__asm__ volatile ("sync");
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} else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
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/* make sure that we access a mirrored address */
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*(volatile u16 *)CFG_CS2_START = 0x1111;
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__asm__ volatile ("sync");
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if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
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/* SRAM size = 512 kByte */
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*(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
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0x80000);
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__asm__ volatile ("sync");
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puts ("SRAM: 512 kB\n");
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}
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else
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puts ("!! possible error in SRAM detection\n");
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} else {
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puts ("SRAM: 1 MB\n");
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}
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/* restore origianl SRAM content */
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if (restore) {
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*(volatile u16 *)CFG_CS2_START = save;
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__asm__ volatile ("sync");
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}
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/*
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* Check for Grafic Controller
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*/
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/* save origianl FB content */
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save = *(volatile u16 *)CFG_CS1_START;
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restore = 1;
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/* write test pattern to FB memory */
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*(volatile u16 *)CFG_CS1_START = 0xA5A5;
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__asm__ volatile ("sync");
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/*
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* Put a different pattern on the data lines: otherwise they may float
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* long enough to read back what we wrote.
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*/
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tmp = *(volatile u16 *)CFG_FLASH_BASE;
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if (tmp == 0xA5A5)
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puts ("!! possible error in grafic controller detection\n");
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if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
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/* no grafic controller at all, disable cs */
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*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
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*(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
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*(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
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restore = 0;
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__asm__ volatile ("sync");
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} else {
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puts ("VGA: SMI501 (Voyager) with 8 MB\n");
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}
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/* restore origianl FB content */
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if (restore) {
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*(volatile u16 *)CFG_CS1_START = save;
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__asm__ volatile ("sync");
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}
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return 0;
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}
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#ifdef CONFIG_VIDEO_SM501
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#define DISPLAY_WIDTH 640
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#define DISPLAY_HEIGHT 480
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#ifdef CONFIG_VIDEO_SM501_8BPP
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#error CONFIG_VIDEO_SM501_8BPP not supported.
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#endif /* CONFIG_VIDEO_SM501_8BPP */
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#ifdef CONFIG_VIDEO_SM501_16BPP
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#error CONFIG_VIDEO_SM501_16BPP not supported.
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#endif /* CONFIG_VIDEO_SM501_16BPP */
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#ifdef CONFIG_VIDEO_SM501_32BPP
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static const SMI_REGS init_regs [] =
|
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{
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#if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT)
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/* FP only */
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{0x00004, 0x0},
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{0x00048, 0x00021807},
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{0x0004C, 0x091a0a01},
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{0x00054, 0x1},
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{0x00040, 0x00021807},
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{0x00044, 0x091a0a01},
|
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{0x00054, 0x0},
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{0x80000, 0x01013106},
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{0x80004, 0xc428bb17},
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{0x80000, 0x03013106},
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{0x8000C, 0x00000000},
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{0x80010, 0x0a000a00},
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{0x80014, 0x02800000},
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{0x80018, 0x01e00000},
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{0x8001C, 0x00000000},
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|
{0x80020, 0x01e00280},
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{0x80024, 0x02fa027f},
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{0x80028, 0x004a028b},
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|
{0x8002C, 0x020c01df},
|
|
{0x80030, 0x000201e9},
|
|
{0x80200, 0x00010200},
|
|
{0x80000, 0x0f013106},
|
|
#elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP)
|
|
/* CRT only */
|
|
{0x00004, 0x0},
|
|
{0x00048, 0x00021807},
|
|
{0x0004C, 0x10090a01},
|
|
{0x00054, 0x1},
|
|
{0x00040, 0x00021807},
|
|
{0x00044, 0x10090a01},
|
|
{0x00054, 0x0},
|
|
{0x80200, 0x00010000},
|
|
{0x80204, 0x0},
|
|
{0x80208, 0x0A000A00},
|
|
{0x8020C, 0x02fa027f},
|
|
{0x80210, 0x004a028b},
|
|
{0x80214, 0x020c01df},
|
|
{0x80218, 0x000201e9},
|
|
{0x80200, 0x00013306},
|
|
#else /* panel + CRT */
|
|
{0x00004, 0x0},
|
|
{0x00048, 0x00021807},
|
|
{0x0004C, 0x091a0a01},
|
|
{0x00054, 0x1},
|
|
{0x00040, 0x00021807},
|
|
{0x00044, 0x091a0a01},
|
|
{0x00054, 0x0},
|
|
{0x80000, 0x0f013106},
|
|
{0x80004, 0xc428bb17},
|
|
{0x8000C, 0x00000000},
|
|
{0x80010, 0x0a000a00},
|
|
{0x80014, 0x02800000},
|
|
{0x80018, 0x01e00000},
|
|
{0x8001C, 0x00000000},
|
|
{0x80020, 0x01e00280},
|
|
{0x80024, 0x02fa027f},
|
|
{0x80028, 0x004a028b},
|
|
{0x8002C, 0x020c01df},
|
|
{0x80030, 0x000201e9},
|
|
{0x80200, 0x00010000},
|
|
#endif
|
|
{0, 0}
|
|
};
|
|
#endif /* CONFIG_VIDEO_SM501_32BPP */
|
|
|
|
#ifdef CONFIG_CONSOLE_EXTRA_INFO
|
|
/*
|
|
* Return text to be printed besides the logo.
|
|
*/
|
|
void video_get_info_str (int line_number, char *info)
|
|
{
|
|
if (line_number == 1) {
|
|
#if defined (CONFIG_TQM5200)
|
|
strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
|
|
#else
|
|
#error No supported board selected
|
|
#endif /* CONFIG_TQM5200 */
|
|
|
|
#if defined (CONFIG_BC3450)
|
|
} else if (line_number == 2) {
|
|
strcpy (info, " Dev: GERSYS BC3450");
|
|
#endif /* CONFIG_BC3450 */
|
|
}
|
|
else {
|
|
info [0] = '\0';
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Returns SM501 register base address. First thing called in the
|
|
* driver. Checks if SM501 is physically present.
|
|
*/
|
|
unsigned int board_video_init (void)
|
|
{
|
|
u16 save, tmp;
|
|
int restore, ret;
|
|
|
|
/*
|
|
* Check for Grafic Controller
|
|
*/
|
|
|
|
/* save origianl FB content */
|
|
save = *(volatile u16 *)CFG_CS1_START;
|
|
restore = 1;
|
|
|
|
/* write test pattern to FB memory */
|
|
*(volatile u16 *)CFG_CS1_START = 0xA5A5;
|
|
__asm__ volatile ("sync");
|
|
/*
|
|
* Put a different pattern on the data lines: otherwise they may float
|
|
* long enough to read back what we wrote.
|
|
*/
|
|
tmp = *(volatile u16 *)CFG_FLASH_BASE;
|
|
if (tmp == 0xA5A5)
|
|
puts ("!! possible error in grafic controller detection\n");
|
|
|
|
if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
|
|
/* no grafic controller found */
|
|
restore = 0;
|
|
ret = 0;
|
|
} else {
|
|
ret = SM501_MMIO_BASE;
|
|
}
|
|
|
|
if (restore) {
|
|
*(volatile u16 *)CFG_CS1_START = save;
|
|
__asm__ volatile ("sync");
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Returns SM501 framebuffer address
|
|
*/
|
|
unsigned int board_video_get_fb (void)
|
|
{
|
|
return SM501_FB_BASE;
|
|
}
|
|
|
|
/*
|
|
* Called after initializing the SM501 and before clearing the screen.
|
|
*/
|
|
void board_validate_screen (unsigned int base)
|
|
{
|
|
}
|
|
|
|
/*
|
|
* Return a pointer to the initialization sequence.
|
|
*/
|
|
const SMI_REGS *board_get_regs (void)
|
|
{
|
|
return init_regs;
|
|
}
|
|
|
|
int board_get_width (void)
|
|
{
|
|
return DISPLAY_WIDTH;
|
|
}
|
|
|
|
int board_get_height (void)
|
|
{
|
|
return DISPLAY_HEIGHT;
|
|
}
|
|
|
|
#endif /* CONFIG_VIDEO_SM501 */
|
|
|