upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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93 lines
2.6 KiB
93 lines
2.6 KiB
/*
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* (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
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* Rohit Choraria <rohitkc@ti.com>
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*
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* (C) Copyright 2013 Andreas Bießmann <andreas.devel@googlemail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_OMAP_GPMC_H
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#define __ASM_OMAP_GPMC_H
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#define GPMC_BUF_EMPTY 0
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#define GPMC_BUF_FULL 1
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#define GPMC_MAX_SECTORS 8
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enum omap_ecc {
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/* 1-bit ECC calculation by Software, Error detection by Software */
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OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */
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/* 1-bit ECC calculation by GPMC, Error detection by Software */
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/* ECC layout compatible to legacy ROMCODE. */
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OMAP_ECC_HAM1_CODE_HW,
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/* 4-bit ECC calculation by GPMC, Error detection by Software */
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OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
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/* 4-bit ECC calculation by GPMC, Error detection by ELM */
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OMAP_ECC_BCH4_CODE_HW,
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/* 8-bit ECC calculation by GPMC, Error detection by Software */
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OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
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/* 8-bit ECC calculation by GPMC, Error detection by ELM */
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OMAP_ECC_BCH8_CODE_HW,
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/* 16-bit ECC calculation by GPMC, Error detection by ELM */
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OMAP_ECC_BCH16_CODE_HW,
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};
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struct gpmc_cs {
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u32 config1; /* 0x00 */
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u32 config2; /* 0x04 */
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u32 config3; /* 0x08 */
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u32 config4; /* 0x0C */
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u32 config5; /* 0x10 */
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u32 config6; /* 0x14 */
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u32 config7; /* 0x18 */
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u32 nand_cmd; /* 0x1C */
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u32 nand_adr; /* 0x20 */
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u32 nand_dat; /* 0x24 */
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u8 res[8]; /* blow up to 0x30 byte */
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};
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struct bch_res_0_3 {
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u32 bch_result_x[4];
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};
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struct bch_res_4_6 {
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u32 bch_result_x[3];
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};
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struct gpmc {
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u8 res1[0x10];
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u32 sysconfig; /* 0x10 */
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u8 res2[0x4];
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u32 irqstatus; /* 0x18 */
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u32 irqenable; /* 0x1C */
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u8 res3[0x20];
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u32 timeout_control; /* 0x40 */
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u8 res4[0xC];
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u32 config; /* 0x50 */
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u32 status; /* 0x54 */
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u8 res5[0x8]; /* 0x58 */
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struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
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u8 res6[0x14]; /* 0x1E0 */
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u32 ecc_config; /* 0x1F4 */
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u32 ecc_control; /* 0x1F8 */
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u32 ecc_size_config; /* 0x1FC */
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u32 ecc1_result; /* 0x200 */
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u32 ecc2_result; /* 0x204 */
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u32 ecc3_result; /* 0x208 */
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u32 ecc4_result; /* 0x20C */
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u32 ecc5_result; /* 0x210 */
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u32 ecc6_result; /* 0x214 */
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u32 ecc7_result; /* 0x218 */
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u32 ecc8_result; /* 0x21C */
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u32 ecc9_result; /* 0x220 */
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u8 res7[12]; /* 0x224 */
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u32 testmomde_ctrl; /* 0x230 */
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u8 res8[12]; /* 0x234 */
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struct bch_res_0_3 bch_result_0_3[GPMC_MAX_SECTORS]; /* 0x240,0x250, */
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u8 res9[16 * 4]; /* 0x2C0 - 0x2FF */
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struct bch_res_4_6 bch_result_4_6[GPMC_MAX_SECTORS]; /* 0x300,0x310, */
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};
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/* Used for board specific gpmc initialization */
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extern struct gpmc *gpmc_cfg;
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#endif /* __ASM_OMAP_GPMC_H */
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