upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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64 lines
1.5 KiB
64 lines
1.5 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2010-2017 CS Systemes d'Information
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* Florent Trinh Thai <florent.trinh-thai@c-s.fr>
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* Christophe Leroy <christophe.leroy@c-s.fr>
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*/
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#include <config.h>
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#include <common.h>
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#include <nand.h>
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#include <asm/io.h>
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#define BIT_CLE ((unsigned short)0x0800)
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#define BIT_ALE ((unsigned short)0x0400)
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#define BIT_NCE ((unsigned short)0x1000)
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static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd_to_nand(mtdinfo);
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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unsigned short pddat = 0;
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/* The hardware control change */
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if (ctrl & NAND_CTRL_CHANGE) {
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pddat = in_be16(&immr->im_ioport.iop_pddat);
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/* Clearing ALE and CLE */
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pddat &= ~(BIT_CLE | BIT_ALE);
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/* Driving NCE pin */
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if (ctrl & NAND_NCE)
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pddat &= ~BIT_NCE;
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else
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pddat |= BIT_NCE;
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/* Driving CLE and ALE pin */
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if (ctrl & NAND_CLE)
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pddat |= BIT_CLE;
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if (ctrl & NAND_ALE)
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pddat |= BIT_ALE;
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out_be16(&immr->im_ioport.iop_pddat, pddat);
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}
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/* Writing the command */
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if (cmd != NAND_CMD_NONE)
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out_8(this->IO_ADDR_W, cmd);
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}
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int board_nand_init(struct nand_chip *nand)
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{
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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/* Set GPIO Port */
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setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00);
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clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00);
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clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000);
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nand->chip_delay = 60;
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nand->ecc.mode = NAND_ECC_SOFT;
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nand->cmd_ctrl = nand_hwcontrol;
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return 0;
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}
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