upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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336 lines
7.9 KiB
336 lines
7.9 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2011
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* Logic Product Development <www.logicpd.com>
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*
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* Author :
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* Peter Barada <peter.barada@logicpd.com>
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*
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* Derived from Beagle Board and 3430 SDP code by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <ns16550.h>
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#include <netdev.h>
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#include <flash.h>
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#include <nand.h>
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#include <i2c.h>
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#include <twl4030.h>
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#include <asm/io.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-types.h>
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#include <linux/mtd/rawnand.h>
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#include <asm/omap_musb.h>
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#include <linux/errno.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/usb/musb.h>
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#include "omap3logic.h"
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#ifdef CONFIG_USB_EHCI_HCD
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#include <usb.h>
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#include <asm/ehci-omap.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* two dimensional array of strucures containining board name and Linux
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* machine IDs; row it selected based on CPU column is slected based
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* on hsusb0_data5 pin having a pulldown resistor
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*/
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static struct board_id {
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char *name;
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int machine_id;
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char *fdtfile;
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} boards[2][2] = {
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{
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{
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.name = "OMAP35xx SOM LV",
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.machine_id = MACH_TYPE_OMAP3530_LV_SOM,
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.fdtfile = "logicpd-som-lv-35xx-devkit.dtb",
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},
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{
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.name = "OMAP35xx Torpedo",
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.machine_id = MACH_TYPE_OMAP3_TORPEDO,
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.fdtfile = "logicpd-torpedo-35xx-devkit.dtb",
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},
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},
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{
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{
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.name = "DM37xx SOM LV",
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.fdtfile = "logicpd-som-lv-37xx-devkit.dtb",
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},
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{
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.name = "DM37xx Torpedo",
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.fdtfile = "logicpd-torpedo-37xx-devkit.dtb",
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},
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},
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};
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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return serial_tstc() && serial_getc() == 'c';
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}
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#endif
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#if defined(CONFIG_SPL_BUILD)
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/*
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* Routine: get_board_mem_timings
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* Description: If we use SPL then there is no x-loader nor config header
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* so we have to setup the DDR timings ourself on the first bank. This
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* provides the timing values back to the function that configures
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* the memory.
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*/
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void get_board_mem_timings(struct board_sdrc_timings *timings)
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{
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timings->mr = MICRON_V_MR_165;
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/* 256MB DDR */
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timings->mcfg = MICRON_V_MCFG_200(256 << 20);
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timings->ctrla = MICRON_V_ACTIMA_200;
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timings->ctrlb = MICRON_V_ACTIMB_200;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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}
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#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
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#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
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#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)
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void spl_board_prepare_for_linux(void)
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{
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/* The Micron NAND starts locked which
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* prohibits mounting the NAND as RW
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* The following commands are what unlocks
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* the NAND to become RW Falcon Mode does not
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* have as many smarts as U-Boot, but Logic PD
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* only makes NAND with 512MB so these hard coded
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* values should work for all current models
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*/
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writeb(0x70, GPMC_NAND_COMMAND_0);
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writeb(-1, GPMC_NAND_DATA_0);
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writeb(0x7a, GPMC_NAND_COMMAND_0);
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writeb(0x00, GPMC_NAND_ADDRESS_0);
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writeb(0x00, GPMC_NAND_ADDRESS_0);
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writeb(0x00, GPMC_NAND_ADDRESS_0);
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writeb(-1, GPMC_NAND_COMMAND_0);
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/* Begin address 0 */
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writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
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writeb(0x00, GPMC_NAND_ADDRESS_0);
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writeb(0x00, GPMC_NAND_ADDRESS_0);
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writeb(0x00, GPMC_NAND_ADDRESS_0);
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writeb(-1, GPMC_NAND_DATA_0);
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/* Ending address at the end of Flash */
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writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
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writeb(0xc0, GPMC_NAND_ADDRESS_0);
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writeb(0xff, GPMC_NAND_ADDRESS_0);
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writeb(0x03, GPMC_NAND_ADDRESS_0);
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writeb(-1, GPMC_NAND_DATA_0);
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writeb(0x79, GPMC_NAND_COMMAND_0);
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writeb(-1, GPMC_NAND_DATA_0);
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writeb(-1, GPMC_NAND_DATA_0);
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}
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#endif
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#ifdef CONFIG_USB_MUSB_OMAP2PLUS
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static struct musb_hdrc_config musb_config = {
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.multipoint = 1,
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.dyn_fifo = 1,
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.num_eps = 16,
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.ram_bits = 12,
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};
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static struct omap_musb_board_data musb_board_data = {
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.interface_type = MUSB_INTERFACE_ULPI,
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};
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static struct musb_hdrc_platform_data musb_plat = {
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#if defined(CONFIG_USB_MUSB_HOST)
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.mode = MUSB_HOST,
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#elif defined(CONFIG_USB_MUSB_GADGET)
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.mode = MUSB_PERIPHERAL,
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#else
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#error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
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#endif
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.config = &musb_config,
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.power = 100,
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.platform_ops = &omap2430_ops,
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.board_data = &musb_board_data,
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};
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#endif
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#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
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/* Call usb_stop() before starting the kernel */
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void show_boot_progress(int val)
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{
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if (val == BOOTSTAGE_ID_RUN_OS)
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usb_stop();
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}
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static struct omap_usbhs_board_data usbhs_bdata = {
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.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
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};
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
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}
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int ehci_hcd_stop(int index)
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{
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return omap_ehci_hcd_stop();
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}
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#endif /* CONFIG_USB_EHCI_HCD */
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/*
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* Routine: misc_init_r
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* Description: Configure board specific parts
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*/
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int misc_init_r(void)
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{
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twl4030_power_init();
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omap_die_id_display();
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#ifdef CONFIG_USB_MUSB_OMAP2PLUS
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musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
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#endif
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return 0;
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}
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/*
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* BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
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*/
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#define BOARD_ID_GPIO 189 /* hsusb0_data5 pin */
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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static void unlock_nand(void)
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{
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int dev = nand_curr_device;
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struct mtd_info *mtd;
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mtd = get_nand_dev_by_index(dev);
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nand_unlock(mtd, 0, mtd->size, 0);
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}
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int board_late_init(void)
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{
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struct board_id *board;
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unsigned int val;
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/*
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* To identify between a SOM LV and Torpedo module,
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* a pulldown resistor is on hsusb0_data5 for the SOM LV module.
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* Drive the pin (and let it soak), then read it back.
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* If the pin is still high its a Torpedo. If low its a SOM LV
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*/
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/* Mux hsusb0_data5 as a GPIO */
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MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4));
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if (gpio_request(BOARD_ID_GPIO, "husb0_data5.gpio_189") == 0) {
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/*
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* Drive BOARD_ID_GPIO - the pulldown resistor on the SOM LV
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* will drain the voltage.
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*/
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gpio_direction_output(BOARD_ID_GPIO, 0);
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gpio_set_value(BOARD_ID_GPIO, 1);
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/* Let it soak for a bit */
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sdelay(0x100);
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/*
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* Read state of BOARD_ID_GPIO as an input and if its set.
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* If so the board is a Torpedo
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*/
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gpio_direction_input(BOARD_ID_GPIO);
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val = gpio_get_value(BOARD_ID_GPIO);
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gpio_free(BOARD_ID_GPIO);
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board = &boards[!!(get_cpu_family() == CPU_OMAP36XX)][!!val];
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printf("Board: %s\n", board->name);
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/* Set the machine_id passed to Linux */
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if (board->machine_id)
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gd->bd->bi_arch_number = board->machine_id;
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/* If the user has not set fdtimage, set the default */
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if (!env_get("fdtimage"))
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env_set("fdtimage", board->fdtfile);
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}
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/* restore hsusb0_data5 pin as hsusb0_data5 */
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MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
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#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
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unlock_nand();
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#endif
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return 0;
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}
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#endif
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#if defined(CONFIG_MMC)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0, -1, -1);
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}
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#endif
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#if defined(CONFIG_MMC)
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void board_mmc_power_init(void)
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{
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twl4030_power_mmc_init(0);
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}
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#endif
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#ifdef CONFIG_SMC911X
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/* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
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static const u32 gpmc_lan92xx_config[] = {
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NET_LAN92XX_GPMC_CONFIG1,
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NET_LAN92XX_GPMC_CONFIG2,
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NET_LAN92XX_GPMC_CONFIG3,
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NET_LAN92XX_GPMC_CONFIG4,
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NET_LAN92XX_GPMC_CONFIG5,
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NET_LAN92XX_GPMC_CONFIG6,
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};
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int board_eth_init(bd_t *bis)
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{
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enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
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CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
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return smc911x_initialize(0, CONFIG_SMC911X_BASE);
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}
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#endif
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