upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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514 lines
14 KiB
514 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014 Samsung Electronics
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* Przemyslaw Marczak <p.marczak@samsung.com>
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*/
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#include <common.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/power.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/gpio.h>
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#include <asm/arch/cpu.h>
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#include <dm.h>
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#include <power/pmic.h>
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#include <power/regulator.h>
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#include <power/max77686_pmic.h>
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#include <errno.h>
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#include <mmc.h>
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#include <usb.h>
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#include <usb/dwc2_udc.h>
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#include <samsung/misc.h>
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#include "setup.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_BOARD_TYPES
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/* Odroid board types */
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enum {
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ODROID_TYPE_U3,
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ODROID_TYPE_X2,
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ODROID_TYPES,
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};
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void set_board_type(void)
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{
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/* Set GPA1 pin 1 to HI - enable XCL205 output */
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writel(XCL205_EN_GPIO_CON_CFG, XCL205_EN_GPIO_CON);
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writel(XCL205_EN_GPIO_DAT_CFG, XCL205_EN_GPIO_CON + 0x4);
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writel(XCL205_EN_GPIO_PUD_CFG, XCL205_EN_GPIO_CON + 0x8);
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writel(XCL205_EN_GPIO_DRV_CFG, XCL205_EN_GPIO_CON + 0xc);
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/* Set GPC1 pin 2 to IN - check XCL205 output state */
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writel(XCL205_STATE_GPIO_CON_CFG, XCL205_STATE_GPIO_CON);
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writel(XCL205_STATE_GPIO_PUD_CFG, XCL205_STATE_GPIO_CON + 0x8);
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/* XCL205 - needs some latch time */
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sdelay(200000);
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/* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
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if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN))
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gd->board_type = ODROID_TYPE_X2;
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else
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gd->board_type = ODROID_TYPE_U3;
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}
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const char *get_board_type(void)
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{
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const char *board_type[] = {"u3", "x2"};
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return board_type[gd->board_type];
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}
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#endif
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#ifdef CONFIG_SET_DFU_ALT_INFO
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char *get_dfu_alt_system(char *interface, char *devstr)
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{
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return env_get("dfu_alt_system");
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}
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char *get_dfu_alt_boot(char *interface, char *devstr)
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{
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struct mmc *mmc;
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char *alt_boot;
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int dev_num;
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dev_num = simple_strtoul(devstr, NULL, 10);
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mmc = find_mmc_device(dev_num);
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if (!mmc)
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return NULL;
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if (mmc_init(mmc))
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return NULL;
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alt_boot = IS_SD(mmc) ? CONFIG_DFU_ALT_BOOT_SD :
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CONFIG_DFU_ALT_BOOT_EMMC;
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return alt_boot;
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}
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#endif
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static void board_clock_init(void)
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{
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unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
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struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
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samsung_get_base_clock();
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/*
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* CMU_CPU clocks src to MPLL
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* Bit values: 0 ; 1
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* MUX_APLL_SEL: FIN_PLL ; FOUT_APLL
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* MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL
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* MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
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* MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
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*/
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clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) |
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MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1);
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set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |
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MUX_MPLL_USER_SEL_C(1);
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clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
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/* Wait for mux change */
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while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
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continue;
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/* Set APLL to 1000MHz */
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clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1);
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set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1);
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clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
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/* Wait for PLL to be locked */
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while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
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continue;
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/* Set CMU_CPU clocks src to APLL */
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set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
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MUX_MPLL_USER_SEL_C(1);
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clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
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/* Wait for mux change */
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while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
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continue;
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set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |
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PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
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APLL_RATIO(0) | CORE2_RATIO(0);
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/*
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* Set dividers for MOUTcore = 1000 MHz
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* coreout = MOUT / (ratio + 1) = 1000 MHz (0)
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* corem0 = armclk / (ratio + 1) = 333 MHz (2)
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* corem1 = armclk / (ratio + 1) = 166 MHz (5)
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* periph = armclk / (ratio + 1) = 1000 MHz (0)
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* atbout = MOUT / (ratio + 1) = 200 MHz (4)
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* pclkdbgout = atbout / (ratio + 1) = 100 MHz (1)
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* sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0)
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* core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk)
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*/
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clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) |
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PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) |
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APLL_RATIO(7) | CORE2_RATIO(7);
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clrsetbits_le32(&clk->div_cpu0, clr, set);
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/* Wait for divider ready status */
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while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
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continue;
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/*
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* For MOUThpm = 1000 MHz (MOUTapll)
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* doutcopy = MOUThpm / (ratio + 1) = 200 (4)
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* sclkhpm = doutcopy / (ratio + 1) = 200 (4)
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* cores_out = armclk / (ratio + 1) = 200 (4)
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*/
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clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
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set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4);
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clrsetbits_le32(&clk->div_cpu1, clr, set);
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/* Wait for divider ready status */
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while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)
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continue;
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/*
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* Set CMU_DMC clocks src to APLL
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* Bit values: 0 ; 1
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* MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL
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* MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL
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* MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL
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* MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT
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* MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
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* MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
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* MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
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* MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1
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*/
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clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) |
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MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) |
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MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) |
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MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
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set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) |
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MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) |
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MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
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clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
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/* Wait for mux change */
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while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
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continue;
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/* Set MPLL to 800MHz */
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set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
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clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
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/* Wait for PLL to be locked */
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while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
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continue;
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/* Switch back CMU_DMC mux */
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set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |
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MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) |
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MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
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clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
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/* Wait for mux change */
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while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
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continue;
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/* CLK_DIV_DMC0 */
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clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) |
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DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
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/*
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* For:
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* MOUTdmc = 800 MHz
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* MOUTdphy = 800 MHz
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*
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* aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
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* pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
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* sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
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* sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
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* aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
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* aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
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*/
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set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
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DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
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clrsetbits_le32(&clk->div_dmc0, clr, set);
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/* Wait for divider ready status */
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while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)
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continue;
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/* CLK_DIV_DMC1 */
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clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) |
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C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
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/*
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* For:
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* MOUTg2d = 800 MHz
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* MOUTc2c = 800 Mhz
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* MOUTpwi = 108 MHz
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*
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* sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3)
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* sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
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* aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
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* sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
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*/
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set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) |
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C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
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clrsetbits_le32(&clk->div_dmc1, clr, set);
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/* Wait for divider ready status */
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while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)
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continue;
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/* CLK_SRC_PERIL0 */
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clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) |
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UART3_SEL(15) | UART4_SEL(15);
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/*
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* Set CLK_SRC_PERIL0 clocks src to MPLL
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* src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0);
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* 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL);
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* 8(SCLK_VPLL)
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*
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* Set all to SCLK_MPLL_USER_T
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*/
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set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) |
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UART4_SEL(6);
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clrsetbits_le32(&clk->src_peril0, clr, set);
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/* CLK_DIV_PERIL0 */
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clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
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UART3_RATIO(15) | UART4_RATIO(15);
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/*
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* For MOUTuart0-4: 800MHz
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*
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* SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
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*/
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set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
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UART3_RATIO(7) | UART4_RATIO(7);
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clrsetbits_le32(&clk->div_peril0, clr, set);
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while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)
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continue;
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/* CLK_DIV_FSYS1 */
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clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
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MMC1_PRE_RATIO(255);
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/*
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* For MOUTmmc0-3 = 800 MHz (MPLL)
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*
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* DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
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* sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
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* DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
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* sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
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*/
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set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
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MMC1_PRE_RATIO(1);
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clrsetbits_le32(&clk->div_fsys1, clr, set);
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/* Wait for divider ready status */
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while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
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continue;
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/* CLK_DIV_FSYS2 */
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clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
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MMC3_PRE_RATIO(255);
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/*
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* For MOUTmmc0-3 = 800 MHz (MPLL)
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*
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* DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
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* sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
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* DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
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* sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
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*/
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set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
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MMC3_PRE_RATIO(1);
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clrsetbits_le32(&clk->div_fsys2, clr, set);
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/* Wait for divider ready status */
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while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)
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continue;
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/* CLK_DIV_FSYS3 */
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clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
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/*
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* For MOUTmmc4 = 800 MHz (MPLL)
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*
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* DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
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* sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
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*/
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set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
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clrsetbits_le32(&clk->div_fsys3, clr, set);
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/* Wait for divider ready status */
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while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)
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continue;
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return;
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}
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static void board_gpio_init(void)
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{
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/* eMMC Reset Pin */
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gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset");
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gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
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gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
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gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
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/* Enable FAN (Odroid U3) */
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gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control");
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gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
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gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
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gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
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/* OTG Vbus output (Odroid U3+) */
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gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus");
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gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE);
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gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X);
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gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
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/* OTG INT (Odroid U3+) */
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gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT");
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gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
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gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
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gpio_direction_input(EXYNOS4X12_GPIO_X31);
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/* Blue LED (Odroid X2/U2/U3) */
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gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED");
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gpio_direction_output(EXYNOS4X12_GPIO_C10, 0);
|
|
|
|
#ifdef CONFIG_CMD_USB
|
|
/* USB3503A Reference frequency */
|
|
gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq");
|
|
|
|
/* USB3503A Connect */
|
|
gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect");
|
|
|
|
/* USB3503A Reset */
|
|
gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset");
|
|
#endif
|
|
}
|
|
|
|
int exynos_early_init_f(void)
|
|
{
|
|
board_clock_init();
|
|
|
|
return 0;
|
|
}
|
|
|
|
int exynos_init(void)
|
|
{
|
|
board_gpio_init();
|
|
|
|
return 0;
|
|
}
|
|
|
|
int exynos_power_init(void)
|
|
{
|
|
const char *mmc_regulators[] = {
|
|
"VDDQ_EMMC_1.8V",
|
|
"VDDQ_EMMC_2.8V",
|
|
"TFLASH_2.8V",
|
|
NULL,
|
|
};
|
|
|
|
if (regulator_list_autoset(mmc_regulators, NULL, true))
|
|
pr_err("Unable to init all mmc regulators");
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_USB_GADGET
|
|
static int s5pc210_phy_control(int on)
|
|
{
|
|
struct udevice *dev;
|
|
int ret;
|
|
|
|
ret = regulator_get_by_platname("VDD_UOTG_3.0V", &dev);
|
|
if (ret) {
|
|
pr_err("Regulator get error: %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
if (on)
|
|
return regulator_set_mode(dev, OPMODE_ON);
|
|
else
|
|
return regulator_set_mode(dev, OPMODE_LPM);
|
|
}
|
|
|
|
struct dwc2_plat_otg_data s5pc210_otg_data = {
|
|
.phy_control = s5pc210_phy_control,
|
|
.regs_phy = EXYNOS4X12_USBPHY_BASE,
|
|
.regs_otg = EXYNOS4X12_USBOTG_BASE,
|
|
.usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
|
|
.usb_flags = PHY0_SLEEP,
|
|
};
|
|
#endif
|
|
|
|
#if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
|
|
|
|
int board_usb_init(int index, enum usb_init_type init)
|
|
{
|
|
#ifdef CONFIG_CMD_USB
|
|
struct udevice *dev;
|
|
int ret;
|
|
|
|
/* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
|
|
/* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
|
|
if (gd->board_type == ODROID_TYPE_U3)
|
|
gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
|
|
else
|
|
gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
|
|
|
|
/* Disconnect, Reset, Connect */
|
|
gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
|
|
gpio_direction_output(EXYNOS4X12_GPIO_X35, 0);
|
|
gpio_direction_output(EXYNOS4X12_GPIO_X35, 1);
|
|
gpio_direction_output(EXYNOS4X12_GPIO_X34, 1);
|
|
|
|
/* Power off and on BUCK8 for LAN9730 */
|
|
debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
|
|
|
|
ret = regulator_get_by_platname("VCC_P3V3_2.85V", &dev);
|
|
if (ret) {
|
|
pr_err("Regulator get error: %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = regulator_set_enable(dev, true);
|
|
if (ret) {
|
|
pr_err("Regulator %s enable setting error: %d", dev->name, ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = regulator_set_value(dev, 750000);
|
|
if (ret) {
|
|
pr_err("Regulator %s value setting error: %d", dev->name, ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = regulator_set_value(dev, 3300000);
|
|
if (ret) {
|
|
pr_err("Regulator %s value setting error: %d", dev->name, ret);
|
|
return ret;
|
|
}
|
|
#endif
|
|
debug("USB_udc_probe\n");
|
|
return dwc2_udc_probe(&s5pc210_otg_data);
|
|
}
|
|
#endif
|
|
|