upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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476 lines
11 KiB
476 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2017 Microchip Technology Inc. All rights reserved.
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*/
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#include <dm.h>
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#include <usb.h>
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#include "usb_ether.h"
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#include "lan7x.h"
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/* LAN78xx specific register/bit defines */
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#define LAN78XX_HW_CFG_LED1_EN BIT(21) /* Muxed with EEDO */
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#define LAN78XX_HW_CFG_LED0_EN BIT(20) /* Muxed with EECLK */
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#define LAN78XX_USB_CFG0 0x080
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#define LAN78XX_USB_CFG0_BIR BIT(6)
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#define LAN78XX_BURST_CAP 0x090
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#define LAN78XX_BULK_IN_DLY 0x094
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#define LAN78XX_RFE_CTL 0x0B0
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#define LAN78XX_FCT_RX_CTL 0x0C0
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#define LAN78XX_FCT_TX_CTL 0x0C4
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#define LAN78XX_FCT_RX_FIFO_END 0x0C8
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#define LAN78XX_FCT_TX_FIFO_END 0x0CC
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#define LAN78XX_FCT_FLOW 0x0D0
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#define LAN78XX_MAF_BASE 0x400
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#define LAN78XX_MAF_HIX 0x00
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#define LAN78XX_MAF_LOX 0x04
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#define LAN78XX_MAF_HI_BEGIN (LAN78XX_MAF_BASE + LAN78XX_MAF_HIX)
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#define LAN78XX_MAF_LO_BEGIN (LAN78XX_MAF_BASE + LAN78XX_MAF_LOX)
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#define LAN78XX_MAF_HI(index) (LAN78XX_MAF_BASE + (8 * (index)) + \
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LAN78XX_MAF_HIX)
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#define LAN78XX_MAF_LO(index) (LAN78XX_MAF_BASE + (8 * (index)) + \
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LAN78XX_MAF_LOX)
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#define LAN78XX_MAF_HI_VALID BIT(31)
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/* OTP registers */
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#define LAN78XX_OTP_BASE_ADDR 0x00001000
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#define LAN78XX_OTP_PWR_DN (LAN78XX_OTP_BASE_ADDR + 4 * 0x00)
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#define LAN78XX_OTP_PWR_DN_PWRDN_N BIT(0)
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#define LAN78XX_OTP_ADDR1 (LAN78XX_OTP_BASE_ADDR + 4 * 0x01)
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#define LAN78XX_OTP_ADDR1_15_11 0x1F
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#define LAN78XX_OTP_ADDR2 (LAN78XX_OTP_BASE_ADDR + 4 * 0x02)
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#define LAN78XX_OTP_ADDR2_10_3 0xFF
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#define LAN78XX_OTP_RD_DATA (LAN78XX_OTP_BASE_ADDR + 4 * 0x06)
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#define LAN78XX_OTP_FUNC_CMD (LAN78XX_OTP_BASE_ADDR + 4 * 0x08)
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#define LAN78XX_OTP_FUNC_CMD_READ BIT(0)
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#define LAN78XX_OTP_CMD_GO (LAN78XX_OTP_BASE_ADDR + 4 * 0x0A)
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#define LAN78XX_OTP_CMD_GO_GO BIT(0)
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#define LAN78XX_OTP_STATUS (LAN78XX_OTP_BASE_ADDR + 4 * 0x0C)
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#define LAN78XX_OTP_STATUS_BUSY BIT(0)
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#define LAN78XX_OTP_INDICATOR_1 0xF3
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#define LAN78XX_OTP_INDICATOR_2 0xF7
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/*
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* Lan78xx infrastructure commands
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*/
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static int lan78xx_read_raw_otp(struct usb_device *udev, u32 offset,
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u32 length, u8 *data)
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{
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int i;
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int ret;
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u32 buf;
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ret = lan7x_read_reg(udev, LAN78XX_OTP_PWR_DN, &buf);
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if (ret)
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return ret;
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if (buf & LAN78XX_OTP_PWR_DN_PWRDN_N) {
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/* clear it and wait to be cleared */
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ret = lan7x_write_reg(udev, LAN78XX_OTP_PWR_DN, 0);
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if (ret)
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return ret;
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ret = lan7x_wait_for_bit(udev, "LAN78XX_OTP_PWR_DN_PWRDN_N",
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LAN78XX_OTP_PWR_DN,
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LAN78XX_OTP_PWR_DN_PWRDN_N,
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false, 1000, 0);
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if (ret)
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return ret;
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}
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for (i = 0; i < length; i++) {
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ret = lan7x_write_reg(udev, LAN78XX_OTP_ADDR1,
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((offset + i) >> 8) &
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LAN78XX_OTP_ADDR1_15_11);
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if (ret)
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return ret;
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ret = lan7x_write_reg(udev, LAN78XX_OTP_ADDR2,
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((offset + i) & LAN78XX_OTP_ADDR2_10_3));
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if (ret)
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return ret;
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ret = lan7x_write_reg(udev, LAN78XX_OTP_FUNC_CMD,
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LAN78XX_OTP_FUNC_CMD_READ);
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if (ret)
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return ret;
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ret = lan7x_write_reg(udev, LAN78XX_OTP_CMD_GO,
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LAN78XX_OTP_CMD_GO_GO);
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if (ret)
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return ret;
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ret = lan7x_wait_for_bit(udev, "LAN78XX_OTP_STATUS_BUSY",
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LAN78XX_OTP_STATUS,
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LAN78XX_OTP_STATUS_BUSY,
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false, 1000, 0);
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if (ret)
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return ret;
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ret = lan7x_read_reg(udev, LAN78XX_OTP_RD_DATA, &buf);
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if (ret)
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return ret;
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data[i] = (u8)(buf & 0xFF);
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}
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return 0;
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}
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static int lan78xx_read_otp(struct usb_device *udev, u32 offset,
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u32 length, u8 *data)
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{
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u8 sig;
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int ret;
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ret = lan78xx_read_raw_otp(udev, 0, 1, &sig);
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if (!ret) {
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if (sig == LAN78XX_OTP_INDICATOR_1)
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offset = offset;
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else if (sig == LAN78XX_OTP_INDICATOR_2)
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offset += 0x100;
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else
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return -EINVAL;
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ret = lan78xx_read_raw_otp(udev, offset, length, data);
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if (ret)
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return ret;
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}
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debug("LAN78x: MAC address from OTP = %pM\n", data);
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return ret;
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}
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static int lan78xx_read_otp_mac(unsigned char *enetaddr,
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struct usb_device *udev)
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{
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int ret;
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memset(enetaddr, 0, 6);
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ret = lan78xx_read_otp(udev,
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EEPROM_MAC_OFFSET,
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ETH_ALEN,
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enetaddr);
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if (!ret && is_valid_ethaddr(enetaddr)) {
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/* eeprom values are valid so use them */
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debug("MAC address read from OTP %pM\n", enetaddr);
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return 0;
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}
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debug("MAC address read from OTP invalid %pM\n", enetaddr);
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memset(enetaddr, 0, 6);
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return -EINVAL;
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}
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static int lan78xx_update_flowcontrol(struct usb_device *udev,
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struct ueth_data *dev)
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{
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uint32_t flow = 0, fct_flow = 0;
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int ret;
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ret = lan7x_update_flowcontrol(udev, dev, &flow, &fct_flow);
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if (ret)
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return ret;
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ret = lan7x_write_reg(udev, LAN78XX_FCT_FLOW, fct_flow);
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if (ret)
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return ret;
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return lan7x_write_reg(udev, FLOW, flow);
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}
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static int lan78xx_read_mac(unsigned char *enetaddr,
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struct usb_device *udev,
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struct lan7x_private *priv)
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{
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u32 val;
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int ret;
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int saved = 0, done = 0;
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/*
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* Depends on chip, some EEPROM pins are muxed with LED function.
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* disable & restore LED function to access EEPROM.
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*/
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if ((priv->chipid == ID_REV_CHIP_ID_7800) ||
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(priv->chipid == ID_REV_CHIP_ID_7850)) {
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ret = lan7x_read_reg(udev, HW_CFG, &val);
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if (ret)
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return ret;
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saved = val;
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val &= ~(LAN78XX_HW_CFG_LED1_EN | LAN78XX_HW_CFG_LED0_EN);
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ret = lan7x_write_reg(udev, HW_CFG, val);
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if (ret)
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goto restore;
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}
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/*
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* Refer to the doc/README.enetaddr and doc/README.usb for
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* the U-Boot MAC address policy
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*/
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/* try reading mac address from EEPROM, then from OTP */
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ret = lan7x_read_eeprom_mac(enetaddr, udev);
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if (!ret)
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done = 1;
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restore:
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if ((priv->chipid == ID_REV_CHIP_ID_7800) ||
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(priv->chipid == ID_REV_CHIP_ID_7850)) {
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ret = lan7x_write_reg(udev, HW_CFG, saved);
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if (ret)
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return ret;
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}
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/* if the EEPROM mac address is good, then exit */
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if (done)
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return 0;
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/* try reading mac address from OTP if the device is LAN78xx */
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return lan78xx_read_otp_mac(enetaddr, udev);
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}
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static int lan78xx_set_receive_filter(struct usb_device *udev)
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{
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/* No multicast in u-boot for now */
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return lan7x_write_reg(udev, LAN78XX_RFE_CTL,
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RFE_CTL_BCAST_EN | RFE_CTL_DA_PERFECT);
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}
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/* starts the TX path */
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static void lan78xx_start_tx_path(struct usb_device *udev)
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{
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/* Enable Tx at MAC */
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lan7x_write_reg(udev, MAC_TX, MAC_TX_TXEN);
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/* Enable Tx at SCSRs */
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lan7x_write_reg(udev, LAN78XX_FCT_TX_CTL, FCT_TX_CTL_EN);
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}
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/* Starts the Receive path */
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static void lan78xx_start_rx_path(struct usb_device *udev)
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{
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/* Enable Rx at MAC */
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lan7x_write_reg(udev, MAC_RX,
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LAN7X_MAC_RX_MAX_SIZE_DEFAULT |
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MAC_RX_FCS_STRIP | MAC_RX_RXEN);
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/* Enable Rx at SCSRs */
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lan7x_write_reg(udev, LAN78XX_FCT_RX_CTL, FCT_RX_CTL_EN);
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}
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static int lan78xx_basic_reset(struct usb_device *udev,
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struct ueth_data *dev,
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struct lan7x_private *priv)
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{
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int ret;
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u32 val;
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ret = lan7x_basic_reset(udev, dev);
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if (ret)
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return ret;
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/* Keep the chip ID */
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ret = lan7x_read_reg(udev, ID_REV, &val);
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if (ret)
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return ret;
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debug("LAN78xx ID_REV = 0x%08x\n", val);
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priv->chipid = (val & ID_REV_CHIP_ID_MASK) >> 16;
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/* Respond to the IN token with a NAK */
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ret = lan7x_read_reg(udev, LAN78XX_USB_CFG0, &val);
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if (ret)
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return ret;
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val |= LAN78XX_USB_CFG0_BIR;
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return lan7x_write_reg(udev, LAN78XX_USB_CFG0, val);
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}
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int lan78xx_write_hwaddr(struct udevice *dev)
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{
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struct usb_device *udev = dev_get_parent_priv(dev);
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struct eth_pdata *pdata = dev_get_platdata(dev);
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unsigned char *enetaddr = pdata->enetaddr;
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u32 addr_lo = get_unaligned_le32(&enetaddr[0]);
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u32 addr_hi = (u32)get_unaligned_le16(&enetaddr[4]);
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int ret;
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/* set hardware address */
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ret = lan7x_write_reg(udev, RX_ADDRL, addr_lo);
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if (ret)
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return ret;
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ret = lan7x_write_reg(udev, RX_ADDRH, addr_hi);
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if (ret)
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return ret;
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ret = lan7x_write_reg(udev, LAN78XX_MAF_LO(0), addr_lo);
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if (ret)
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return ret;
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ret = lan7x_write_reg(udev, LAN78XX_MAF_HI(0),
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addr_hi | LAN78XX_MAF_HI_VALID);
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if (ret)
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return ret;
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debug("MAC addr %pM written\n", enetaddr);
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return 0;
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}
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static int lan78xx_eth_start(struct udevice *dev)
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{
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struct usb_device *udev = dev_get_parent_priv(dev);
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struct lan7x_private *priv = dev_get_priv(dev);
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int ret;
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u32 write_buf;
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/* Reset and read Mac addr were done in probe() */
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ret = lan78xx_write_hwaddr(dev);
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if (ret)
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return ret;
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ret = lan7x_write_reg(udev, LAN78XX_BURST_CAP, 0);
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if (ret)
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return ret;
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ret = lan7x_write_reg(udev, LAN78XX_BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
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if (ret)
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return ret;
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ret = lan7x_write_reg(udev, INT_STS, 0xFFFFFFFF);
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if (ret)
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return ret;
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/* set FIFO sizes */
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ret = lan7x_write_reg(udev, LAN78XX_FCT_RX_FIFO_END,
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(MAX_RX_FIFO_SIZE - 512) / 512);
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if (ret)
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return ret;
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ret = lan7x_write_reg(udev, LAN78XX_FCT_TX_FIFO_END,
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(MAX_TX_FIFO_SIZE - 512) / 512);
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if (ret)
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return ret;
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/* Init Tx */
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ret = lan7x_write_reg(udev, FLOW, 0);
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if (ret)
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return ret;
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/* Init Rx. Set Vlan, keep default for VLAN on 78xx */
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ret = lan78xx_set_receive_filter(udev);
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if (ret)
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return ret;
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/* Init PHY, autonego, and link */
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ret = lan7x_eth_phylib_connect(dev, &priv->ueth);
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if (ret)
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return ret;
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ret = lan7x_eth_phylib_config_start(dev);
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if (ret)
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return ret;
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/*
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* MAC_CR has to be set after PHY init.
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* MAC will auto detect the PHY speed.
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*/
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ret = lan7x_read_reg(udev, MAC_CR, &write_buf);
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if (ret)
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return ret;
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write_buf |= MAC_CR_AUTO_DUPLEX | MAC_CR_AUTO_SPEED | MAC_CR_ADP;
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ret = lan7x_write_reg(udev, MAC_CR, write_buf);
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if (ret)
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return ret;
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lan78xx_start_tx_path(udev);
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lan78xx_start_rx_path(udev);
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return lan78xx_update_flowcontrol(udev, &priv->ueth);
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}
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int lan78xx_read_rom_hwaddr(struct udevice *dev)
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{
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struct usb_device *udev = dev_get_parent_priv(dev);
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struct eth_pdata *pdata = dev_get_platdata(dev);
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struct lan7x_private *priv = dev_get_priv(dev);
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int ret;
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ret = lan78xx_read_mac(pdata->enetaddr, udev, priv);
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if (ret)
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memset(pdata->enetaddr, 0, 6);
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return 0;
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}
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static int lan78xx_eth_probe(struct udevice *dev)
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{
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struct usb_device *udev = dev_get_parent_priv(dev);
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struct lan7x_private *priv = dev_get_priv(dev);
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struct ueth_data *ueth = &priv->ueth;
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struct eth_pdata *pdata = dev_get_platdata(dev);
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int ret;
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/* Do a reset in order to get the MAC address from HW */
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if (lan78xx_basic_reset(udev, ueth, priv))
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return 0;
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/* Get the MAC address */
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/*
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* We must set the eth->enetaddr from HW because the upper layer
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* will force to use the environmental var (usbethaddr) or random if
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* there is no valid MAC address in eth->enetaddr.
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*/
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lan78xx_read_mac(pdata->enetaddr, udev, priv);
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/* Do not return 0 for not finding MAC addr in HW */
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ret = usb_ether_register(dev, ueth, RX_URB_SIZE);
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if (ret)
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return ret;
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/* Register phylib */
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return lan7x_phylib_register(dev);
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}
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static const struct eth_ops lan78xx_eth_ops = {
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.start = lan78xx_eth_start,
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.send = lan7x_eth_send,
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.recv = lan7x_eth_recv,
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.free_pkt = lan7x_free_pkt,
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.stop = lan7x_eth_stop,
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.write_hwaddr = lan78xx_write_hwaddr,
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.read_rom_hwaddr = lan78xx_read_rom_hwaddr,
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};
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U_BOOT_DRIVER(lan78xx_eth) = {
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.name = "lan78xx_eth",
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.id = UCLASS_ETH,
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.probe = lan78xx_eth_probe,
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.remove = lan7x_eth_remove,
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.ops = &lan78xx_eth_ops,
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.priv_auto_alloc_size = sizeof(struct lan7x_private),
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.platdata_auto_alloc_size = sizeof(struct eth_pdata),
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};
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static const struct usb_device_id lan78xx_eth_id_table[] = {
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{ USB_DEVICE(0x0424, 0x7800) }, /* LAN7800 USB Ethernet */
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{ USB_DEVICE(0x0424, 0x7850) }, /* LAN7850 USB Ethernet */
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{ } /* Terminating entry */
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};
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U_BOOT_USB_DEVICE(lan78xx_eth, lan78xx_eth_id_table);
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