upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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127 lines
3.6 KiB
127 lines
3.6 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017 Synopsys, Inc. All rights reserved.
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*/
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#ifndef _CONFIG_HSDK_H_
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#define _CONFIG_HSDK_H_
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#include <linux/sizes.h>
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/*
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* CPU configuration
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*/
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#define NR_CPUS 4
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#define ARC_PERIPHERAL_BASE 0xF0000000
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#define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
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#define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000)
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/*
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* Memory configuration
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_SDRAM_SIZE SZ_1G
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_MALLOC_LEN SZ_2M
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#define CONFIG_SYS_BOOTM_LEN SZ_128M
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#define CONFIG_SYS_LOAD_ADDR 0x82000000
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/*
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* This board might be of different versions so handle it
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*/
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#define CONFIG_BOARD_TYPES
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/*
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* UART configuration
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*/
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#define CONFIG_DW_SERIAL
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_CLK 33330000
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#define CONFIG_SYS_NS16550_MEM32
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/*
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* Ethernet PHY configuration
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*/
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#define CONFIG_MII
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/*
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* USB 1.1 configuration
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*/
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
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/*
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* Environment settings
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*/
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#define CONFIG_ENV_SIZE SZ_16K
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"core_dccm_0=0x10\0" \
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"core_dccm_1=0x6\0" \
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"core_dccm_2=0x10\0" \
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"core_dccm_3=0x6\0" \
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"core_iccm_0=0x10\0" \
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"core_iccm_1=0x6\0" \
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"core_iccm_2=0x10\0" \
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"core_iccm_3=0x6\0" \
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"core_mask=0xF\0" \
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"dcache_ena=0x1\0" \
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"icache_ena=0x1\0" \
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"non_volatile_limit=0xE\0" \
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"hsdk_hs34=setenv core_mask 0x2; setenv icache_ena 0x0; \
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setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
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setenv core_dccm_1 0x8; setenv non_volatile_limit 0x0;\0" \
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"hsdk_hs36=setenv core_mask 0x1; setenv icache_ena 0x1; \
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setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
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setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
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"hsdk_hs36_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
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setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
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setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
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"hsdk_hs38=setenv core_mask 0x1; setenv icache_ena 0x1; \
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setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
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setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \
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"hsdk_hs38_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \
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setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
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setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \
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"hsdk_hs38x2=setenv core_mask 0x3; setenv icache_ena 0x1; \
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setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
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setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
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setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \
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"hsdk_hs38x3=setenv core_mask 0x7; setenv icache_ena 0x1; \
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setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
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setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
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setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
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setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \
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"hsdk_hs38x4=setenv core_mask 0xF; setenv icache_ena 0x1; \
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setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
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setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \
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setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \
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setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \
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setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0"
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/*
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* Environment configuration
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*/
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
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/*
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* Misc utility configuration
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*/
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#define CONFIG_BOUNCE_BUFFER
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/* Cli configuration */
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#define CONFIG_SYS_CBSIZE SZ_2K
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/*
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* Callback configuration
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*/
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#define CONFIG_BOARD_LATE_INIT
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#endif /* _CONFIG_HSDK_H_ */
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