upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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123 lines
3.2 KiB
123 lines
3.2 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*/
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#ifndef __LS1012AQDS_H__
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#define __LS1012AQDS_H__
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#include "ls1012a_common.h"
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/* DDR */
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#define CONFIG_CHIP_SELECTS_PER_CTRL 1
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#define CONFIG_NR_DRAM_BANKS 2
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#define CONFIG_SYS_SDRAM_SIZE 0x40000000
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#define CONFIG_CMD_MEMINFO
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#define CONFIG_SYS_MEMTEST_START 0x80000000
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#define CONFIG_SYS_MEMTEST_END 0x9fffffff
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/*
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* QIXIS Definitions
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*/
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#define CONFIG_FSL_QIXIS
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#ifdef CONFIG_FSL_QIXIS
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#define CONFIG_QIXIS_I2C_ACCESS
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#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
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#define QIXIS_LBMAP_BRDCFG_REG 0x04
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#define QIXIS_LBMAP_SWITCH 6
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#define QIXIS_LBMAP_MASK 0x08
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#define QIXIS_LBMAP_SHIFT 0
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#define QIXIS_LBMAP_DFLTBANK 0x00
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#define QIXIS_LBMAP_ALTBANK 0x08
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#define QIXIS_RST_CTL_RESET 0x31
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#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
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#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
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#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
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#endif
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/*
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* I2C bus multiplexer
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*/
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#define I2C_MUX_PCA_ADDR_PRI 0x77
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#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
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#define I2C_RETIMER_ADDR 0x18
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#define I2C_MUX_CH_DEFAULT 0x8
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#define I2C_MUX_CH_CH7301 0xC
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#define I2C_MUX_CH5 0xD
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#define I2C_MUX_CH7 0xF
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#define I2C_MUX_CH_VOL_MONITOR 0xa
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/*
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* RTC configuration
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*/
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#define RTC
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#define CONFIG_RTC_PCF8563 1
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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/* Voltage monitor on channel 2*/
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#define I2C_VOL_MONITOR_ADDR 0x40
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#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
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#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
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#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
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/* DSPI */
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#define CONFIG_FSL_DSPI1
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#define CONFIG_DEFAULT_SPI_BUS 1
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#define CONFIG_CMD_SPI
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#define MMAP_DSPI DSPI1_BASE_ADDR
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#define CONFIG_SYS_DSPI_CTAR0 1
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#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
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DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
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DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
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DSPI_CTAR_DT(0))
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#define CONFIG_SPI_FLASH_SST /* cs1 */
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#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
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DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
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DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
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DSPI_CTAR_DT(0))
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#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
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#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
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DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
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DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
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DSPI_CTAR_DT(0))
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#define CONFIG_SPI_FLASH_EON /* cs3 */
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#define CONFIG_SF_DEFAULT_SPEED 10000000
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#define CONFIG_SF_DEFAULT_BUS 1
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#define CONFIG_SF_DEFAULT_CS 0
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/* MMC */
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#ifdef CONFIG_MMC
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#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
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#endif
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#define CONFIG_PCIE1 /* PCIE controller 1 */
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_CMD_MEMINFO
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#define CONFIG_SYS_MEMTEST_START 0x80000000
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#define CONFIG_SYS_MEMTEST_END 0x9fffffff
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#define CONFIG_MISC_INIT_R
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#endif /* __LS1012AQDS_H__ */
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