upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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245 lines
7.6 KiB
245 lines
7.6 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuration for Versatile Express. Parts were derived from other ARM
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* configurations.
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*/
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#ifndef __VEXPRESS_AEMV8A_H
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#define __VEXPRESS_AEMV8A_H
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#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
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#ifndef CONFIG_SEMIHOSTING
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#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
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#endif
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#define CONFIG_ARMV8_SWITCH_TO_EL1
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#endif
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#define CONFIG_REMAKE_ELF
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/* Link Definitions */
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#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
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defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM)
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/* ATF loads u-boot here for BASE_FVP model */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
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#elif CONFIG_TARGET_VEXPRESS64_JUNO
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
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#endif
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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/* CS register bases for the original memory map. */
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#define V2M_PA_CS0 0x00000000
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#define V2M_PA_CS1 0x14000000
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#define V2M_PA_CS2 0x18000000
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#define V2M_PA_CS3 0x1c000000
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#define V2M_PA_CS4 0x0c000000
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#define V2M_PA_CS5 0x10000000
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#define V2M_PERIPH_OFFSET(x) (x << 16)
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#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
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#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
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#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
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#define V2M_BASE 0x80000000
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/* Common peripherals relative to CS7. */
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#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
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#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
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#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
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#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
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#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
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#define V2M_UART0 0x7ff80000
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#define V2M_UART1 0x7ff70000
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#else /* Not Juno */
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#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
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#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
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#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
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#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
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#endif
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#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
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#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
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#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
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#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
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#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
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#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
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#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
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/* System register offsets. */
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#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
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#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
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#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
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/* Generic Interrupt Controller Definitions */
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#ifdef CONFIG_GICV3
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#define GICD_BASE (0x2f000000)
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#define GICR_BASE (0x2f100000)
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#else
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#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
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defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM)
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#define GICD_BASE (0x2f000000)
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#define GICC_BASE (0x2c000000)
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#elif CONFIG_TARGET_VEXPRESS64_JUNO
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#define GICD_BASE (0x2C010000)
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#define GICC_BASE (0x2C02f000)
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#endif
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#endif /* !CONFIG_GICV3 */
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
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#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
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/* The Vexpress64 simulators use SMSC91C111 */
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#define CONFIG_SMC91111 1
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#define CONFIG_SMC91111_BASE (0x01A000000)
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#endif
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/* PL011 Serial Configuration */
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#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
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#define CONFIG_PL011_CLOCK 7273800
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#else
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#define CONFIG_PL011_CLOCK 24000000
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#endif
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/*#define CONFIG_MENU_SHOW*/
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/* BOOTP options */
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#define CONFIG_BOOTP_BOOTFILESIZE
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000)
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/* Physical Memory Map */
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#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
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/* Top 16MB reserved for secure world use */
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#define DRAM_SEC_SIZE 0x01000000
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#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
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#define CONFIG_NR_DRAM_BANKS 2
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#define PHYS_SDRAM_2 (0x880000000)
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#define PHYS_SDRAM_2_SIZE 0x180000000
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#else
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#define CONFIG_NR_DRAM_BANKS 1
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#endif
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/* Enable memtest */
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
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#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
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/* Initial environment variables */
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#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
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/*
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* Defines where the kernel and FDT exist in NOR flash and where it will
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* be copied into DRAM
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"kernel_name=norkern\0" \
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"kernel_alt_name=Image\0" \
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"kernel_addr=0x80080000\0" \
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"initrd_name=ramdisk.img\0" \
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"initrd_addr=0x84000000\0" \
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"fdtfile=board.dtb\0" \
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"fdt_alt_name=juno\0" \
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"fdt_addr=0x83000000\0" \
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"fdt_high=0xffffffffffffffff\0" \
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"initrd_high=0xffffffffffffffff\0" \
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/* Copy the kernel and FDT to DRAM memory and boot */
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#define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \
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"if test $? -eq 1; then "\
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" echo Loading ${kernel_alt_name} instead of "\
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"${kernel_name}; "\
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" afs load ${kernel_alt_name} ${kernel_addr};"\
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"fi ; "\
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"afs load ${fdtfile} ${fdt_addr} ; " \
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"if test $? -eq 1; then "\
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" echo Loading ${fdt_alt_name} instead of "\
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"${fdtfile}; "\
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" afs load ${fdt_alt_name} ${fdt_addr}; "\
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"fi ; "\
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"fdt addr ${fdt_addr}; fdt resize; " \
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"if afs load ${initrd_name} ${initrd_addr} ; "\
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"then "\
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" setenv initrd_param ${initrd_addr}; "\
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" else setenv initrd_param -; "\
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"fi ; " \
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"booti ${kernel_addr} ${initrd_param} ${fdt_addr}"
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#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"kernel_name=Image\0" \
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"kernel_addr=0x80080000\0" \
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"initrd_name=ramdisk.img\0" \
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"initrd_addr=0x88000000\0" \
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"fdtfile=devtree.dtb\0" \
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"fdt_addr=0x83000000\0" \
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"fdt_high=0xffffffffffffffff\0" \
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"initrd_high=0xffffffffffffffff\0"
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#define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \
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"smhload ${fdtfile} ${fdt_addr}; " \
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"smhload ${initrd_name} ${initrd_addr} "\
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"initrd_end; " \
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"fdt addr ${fdt_addr}; fdt resize; " \
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"fdt chosen ${initrd_addr} ${initrd_end}; " \
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"booti $kernel_addr - $fdt_addr"
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#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"kernel_addr=0x80080000\0" \
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"initrd_addr=0x84000000\0" \
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"fdt_addr=0x83000000\0" \
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"fdt_high=0xffffffffffffffff\0" \
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"initrd_high=0xffffffffffffffff\0"
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#define CONFIG_BOOTCOMMAND "booti $kernel_addr $initrd_addr $fdt_addr"
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#endif
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_MAXARGS 64 /* max command args */
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#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
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#define CONFIG_SYS_FLASH_BASE 0x08000000
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/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
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#define CONFIG_SYS_MAX_FLASH_SECT 259
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/* Store environment at top of flash in the same location as blank.img */
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/* in the Juno firmware. */
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#define CONFIG_ENV_ADDR 0x0BFC0000
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#define CONFIG_ENV_SECT_SIZE 0x00010000
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#else
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#define CONFIG_SYS_FLASH_BASE 0x0C000000
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/* 256 x 256KiB sectors */
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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/* Store environment at top of flash */
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#define CONFIG_ENV_ADDR 0x0FFC0000
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#define CONFIG_ENV_SECT_SIZE 0x00040000
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#endif
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
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#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
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#define FLASH_MAX_SECTOR_SIZE 0x00040000
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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#endif /* __VEXPRESS_AEMV8A_H */
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