upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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98 lines
2.7 KiB
98 lines
2.7 KiB
/*
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* Copyright (C) 2009 Texas Instruments Incorporated
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <common.h>
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#include <nand.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/gpio_defs.h>
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#include <asm/arch/nand_defs.h>
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#include "../common/misc.h"
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#include <net.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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struct davinci_gpio *gpio01_base =
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(struct davinci_gpio *)DAVINCI_GPIO_BANK01;
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struct davinci_gpio *gpio23_base =
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(struct davinci_gpio *)DAVINCI_GPIO_BANK23;
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struct davinci_gpio *gpio67_base =
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(struct davinci_gpio *)DAVINCI_GPIO_BANK67;
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gd->bd->bi_arch_number = MACH_TYPE_DM355_LEOPARD;
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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/* GIO 9 & 10 are used for IO */
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writel((readl(PINMUX3) & 0XF8FFFFFF), PINMUX3);
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/* Interrupt set GIO 9 */
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writel((readl(DAVINCI_GPIO_BINTEN) | 0x1), DAVINCI_GPIO_BINTEN);
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/* set GIO 9 input */
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writel((readl(&gpio01_base->dir) | (1 << 9)), &gpio01_base->dir);
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/* Both edge trigger GIO 9 */
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writel((readl(&gpio01_base->set_rising) | (1 << 9)),
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&gpio01_base->set_rising);
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writel((readl(&gpio01_base->dir) & ~(1 << 5)), &gpio01_base->dir);
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/* output low */
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writel((readl(&gpio01_base->set_data) & ~(1 << 5)),
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&gpio01_base->set_data);
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/* set GIO 10 output */
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writel((readl(&gpio01_base->dir) & ~(1 << 10)), &gpio01_base->dir);
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/* output high */
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writel((readl(&gpio01_base->set_data) | (1 << 10)),
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&gpio01_base->set_data);
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/* set GIO 32 output */
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writel((readl(&gpio23_base->dir) & ~(1 << 0)), &gpio23_base->dir);
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/* output High */
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writel((readl(&gpio23_base->set_data) | (1 << 0)),
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&gpio23_base->set_data);
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/* Enable UART1 MUX Lines */
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writel((readl(PINMUX0) & ~3), PINMUX0);
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writel((readl(&gpio67_base->dir) & ~(1 << 6)), &gpio67_base->dir);
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writel((readl(&gpio67_base->set_data) | (1 << 6)),
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&gpio67_base->set_data);
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return 0;
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}
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#ifdef CONFIG_DRIVER_DM9000
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int board_eth_init(bd_t *bis)
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{
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return dm9000_initialize(bis);
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}
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#endif
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#ifdef CONFIG_NAND_DAVINCI
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int board_nand_init(struct nand_chip *nand)
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{
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davinci_nand_init(nand);
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return 0;
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}
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#endif
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