upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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596 lines
20 KiB
596 lines
20 KiB
/*
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* (C) Copyright 2001
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* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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/*************************************************************************
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* (c) 2002 Datentechnik AG - Project: Dino
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*
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*
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* $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $
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*
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************************************************************************/
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/*************************************************************************
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*
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* History:
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*
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* $Log: DB64360.h,v $
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* Revision 1.3 2003/04/26 04:58:13 brad
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* Cosmetic changes and compiler warning cleanups
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*
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* Revision 1.2 2003/04/23 15:48:15 ingo
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* mem. map output added
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*
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* Revision 1.1 2003/04/17 09:31:42 ias
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* keymile changes 17_04_2003
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*
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* Revision 1.10 2003/03/06 12:25:04 ias
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* 750 FX CPU HID settings updated
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*
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* Revision 1.9 2003/03/03 16:14:36 ias
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* cleanup compiler warnings of printf fuctions
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*
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* Revision 1.8 2003/03/03 15:11:44 ias
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* Marvell MPSC-UART is working
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*
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* Revision 1.7 2003/02/26 12:15:45 ssu
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* adapted default parameters to new board flash address
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*
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* Revision 1.6 2003/02/25 14:55:42 ssu
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* changed default environment parameters
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*
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* Revision 1.5 2003/02/21 17:14:23 ias
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* added extended SPD handling
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*
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* Revision 1.4 2003/01/14 09:16:08 ias
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* PPCBoot for Marvel Beta 0.9
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*
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* Revision 1.3 2002/12/03 13:56:26 ias
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* Environment in flash support added
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*
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* Revision 1.2 2002/11/29 16:53:29 ias
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* Flash support for STM added
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*
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* Revision 1.1 2002/11/29 13:36:31 ias
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* Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board
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* - working DDRRAM (only 32MByte of 128MB Modul)
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* - working I2C Driver for SPD EEPROM read
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* - working DUART 16650 for Serial Console
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* - working "console"
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*
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*
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*
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************************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* This define must be before the core.h include */
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#define CONFIG_DB64360 1 /* this is an DB64360 board */
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#ifndef __ASSEMBLY__
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#include "../board/Marvell/include/core.h"
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#endif
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/*-----------------------------------------------------*/
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/* #include "../board/db64360/local.h" */
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#ifndef __LOCAL_H
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#define __LOCAL_H
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/* first ethernet */
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#define CONFIG_ETHADDR 64:36:00:00:00:01
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/* next two ethernet hwaddrs */
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#define CONFIG_HAS_ETH1
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#define CONFIG_ETH1ADDR 64:36:00:00:00:02
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/* in the atlantis 64360 we have only 2 ETH port on the board,
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if we use PCI it has its own MAC addr */
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#define CONFIG_ENV_OVERWRITE
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#endif /* __CONFIG_H */
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_74xx /* we have a 750FX (override local.h) */
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#define CONFIG_DB64360 1 /* this is an DB64360 board */
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#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
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/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
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DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
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so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
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see sdram_init.c */
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#undef CONFIG_ECC /* enable ECC support */
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#define CONFIG_MV64360_ECC
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/* which initialization functions to call for this board */
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#define CONFIG_MISC_INIT_R /* initialize the icache L1 */
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CFG_BOARD_NAME "DB64360"
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#define CONFIG_IDENT_STRING "Marvell DB64360 (1.1)"
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/*#define CFG_HUSH_PARSER */
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#undef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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/*
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* The following defines let you select what serial you want to use
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* for your console driver.
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*
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* what to do:
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* to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
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* cable onto the second DUART channel, change the CFG_DUART port from 1
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* to 0 below.
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*
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* to use the MPSC, #define CONFIG_MPSC. If you have wired up another
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* mpsc channel, change CONFIG_MPSC_PORT to the desired value.
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*/
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#define CONFIG_MPSC_PORT 0
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/* to change the default ethernet port, use this define (options: 0, 1, 2) */
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#define CONFIG_NET_MULTI
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#define MV_ETH_DEVS 2
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/* #undef CONFIG_ETHER_PORT_MII */
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#undef CONFIG_BOOTARGS
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/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */
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/* ronen - autoboot using tftp */
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#if (CONFIG_BOOTDELAY >= 0)
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#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 uImage;\
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setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \
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ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000; "
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#define CONFIG_BOOTARGS "console=ttyS0,115200"
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#endif
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/* ronen - the u-boot.bin should be ~0x30000 bytes */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
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cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
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"burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
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cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
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"bootargs_root=root=/dev/nfs rw\0" \
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"bootargs_end=:::DB64360:eth0:none \0"\
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"ethprime=mv_enet0\0"\
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"standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \
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ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
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/* --------------------------------------------------------------------------------------------------------------- */
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/* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */
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#define CONFIG_IPADDR 10.2.40.90
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#define CONFIG_SERIAL "No. 1"
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#define CONFIG_SERVERIP 10.2.1.126
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#define CONFIG_ROOTPATH /mnt/yellow_dog_mini
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#define CONFIG_TESTDRAMDATA y
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#define CONFIG_TESTDRAMADDRESS n
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#define CONFIG_TESETDRAMWALK n
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/* --------------------------------------------------------------------------------------------------------------- */
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#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
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#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#undef CONFIG_ALTIVEC /* undef to disable */
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
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CONFIG_BOOTP_BOOTFILESIZE)
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/*
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* JFFS2 partitions
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*
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*/
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/* No command line, one static partition, whole device */
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#undef CONFIG_JFFS2_CMDLINE
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#define CONFIG_JFFS2_DEV "nor1"
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#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
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#define CONFIG_JFFS2_PART_OFFSET 0x00000000
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/* mtdparts command line support */
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/* Use first bank for JFFS2, second bank contains U-Boot.
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*
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* Note: fake mtd_id's used, no linux mtd map file.
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*/
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/*
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#define CONFIG_JFFS2_CMDLINE
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#define MTDIDS_DEFAULT "nor1=db64360-1"
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#define MTDPARTS_DEFAULT "mtdparts=db64360-1:-(jffs2)"
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*/
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
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| CFG_CMD_ASKENV \
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| CFG_CMD_I2C \
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| CFG_CMD_EEPROM \
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| CFG_CMD_CACHE \
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| CFG_CMD_JFFS2 \
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| CFG_CMD_PCI \
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| CFG_CMD_NET )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_I2C_MULTI_EEPROMS
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#define CFG_I2C_SPEED 40000 /* I2C speed default */
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/* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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/*#define CFG_MEMTEST_START 0x00400000 memtest works on */
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/*#define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
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/*#define CFG_MEMTEST_END 0x07c00000 4 ... 124 MB in DRAM */
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/*
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#define CFG_DRAM_TEST
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* DRAM tests
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* CFG_DRAM_TEST - enables the following tests.
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*
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* CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
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* Environment variable 'test_dram_data' must be
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* set to 'y'.
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* CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
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* addressable. Environment variable
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* 'test_dram_address' must be set to 'y'.
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* CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
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* This test takes about 6 minutes to test 64 MB.
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* Environment variable 'test_dram_walk' must be
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* set to 'y'.
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*/
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#define CFG_DRAM_TEST
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#if defined(CFG_DRAM_TEST)
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#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
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/* #define CFG_MEMTEST_END 0x00C00000 4 ... 12 MB in DRAM */
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#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
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#define CFG_DRAM_TEST_DATA
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#define CFG_DRAM_TEST_ADDRESS
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#define CFG_DRAM_TEST_WALK
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#endif /* CFG_DRAM_TEST */
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#undef CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
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#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
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#define CFG_LOAD_ADDR 0x00400000 /* default load address */
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#define CFG_HZ 1000 /* decr freq: 1ms ticks */
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/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
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#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
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#define CFG_BUS_CLK CFG_BUS_HZ
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#define CFG_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
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#define CFG_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */
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/*ronen - this is the Tclk (MV64360 core) */
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#define CFG_TCLK 133000000
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#define CFG_750FX_HID0 0x8000c084
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#define CFG_750FX_HID1 0x54800000
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#define CFG_750FX_HID2 0x00000000
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area
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*/
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/*
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* When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
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* To an unused memory region. The stack will remain in cache until RAM
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* is initialized
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*/
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#define CFG_INIT_RAM_LOCK
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#define CFG_INIT_RAM_ADDR 0x40000000 /* unused memory region */
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#define CFG_INIT_RAM_END 0x1000
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define RELOCATE_INTERNAL_RAM_ADDR
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#ifdef RELOCATE_INTERNAL_RAM_ADDR
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#define CFG_INTERNAL_RAM_ADDR 0xf8000000
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#endif
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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/* Dummies for BAT 4-7 */
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#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */
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#define CFG_SDRAM2_BASE 0x20000000
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#define CFG_SDRAM3_BASE 0x30000000
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#define CFG_SDRAM4_BASE 0x40000000
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#define CFG_FLASH_BASE 0xfff00000
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#define CFG_DFL_BOOTCS_BASE 0xff800000
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#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS*/
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#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
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#define UART_BASE_BOOTM 0xfbb00000 /* in order to be sync with the kernel parameters. */
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#define PCI0_IO_BASE_BOOTM 0xfd000000
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#define CFG_RESET_ADDRESS 0xfff00100
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
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/* areas to map different things with the GT in physical space */
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#define CFG_DRAM_BANKS 4
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/* What to put in the bats. */
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#define CFG_MISC_REGION_BASE 0xf0000000
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/* Peripheral Device section */
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/*******************************************************/
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/* We have on the db64360 Board : */
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/* GT-Chipset Register Area */
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/* GT-Chipset internal SRAM 256k */
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/* SRAM on external device module */
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/* Real time clock on external device module */
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/* dobble UART on external device module */
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/* Data flash on external device module */
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/* Boot flash on external device module */
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/*******************************************************/
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#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
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#define CFG_DB64360_RESET_ADDR 0x14000000 /* After power on Reset the DB64360 is here */
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/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
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#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
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#define CFG_DEV_BASE 0xfc000000 /* GT Devices CS start here */
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#define CFG_DEV0_SPACE CFG_DEV_BASE /* DEV_CS0 device modul sram */
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#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE) /* DEV_CS1 device modul real time clock (rtc) */
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#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE) /* DEV_CS2 device modul doubel uart (duart) */
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#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE) /* DEV_CS3 device modul large flash */
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#define CFG_DEV0_SIZE _8M /* db64360 sram @ 0xfc00.0000 */
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#define CFG_DEV1_SIZE _8M /* db64360 rtc @ 0xfc80.0000 */
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#define CFG_DEV2_SIZE _16M /* db64360 duart @ 0xfd00.0000 */
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#define CFG_DEV3_SIZE _16M /* db64360 flash @ 0xfe00.0000 */
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/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
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/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
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#define CFG_DEV0_PAR 0x8FEFFFFF /* 32Bit sram */
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#define CFG_DEV1_PAR 0x8FCFFFFF /* 8Bit rtc */
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#define CFG_DEV2_PAR 0x8FCFFFFF /* 8Bit duart */
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#define CFG_8BIT_BOOT_PAR 0x8FCFFFFF /* 8Bit flash */
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#define CFG_32BIT_BOOT_PAR 0x8FEFFFFF /* 32Bit flash */
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/* c 4 a 8 2 4 1 c */
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/* 33 22|2222|22 22|111 1|11 11|1 1 | | */
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/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
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/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
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/* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
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/* ronen - update MPP Control MV64360*/
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#define CFG_MPP_CONTROL_0 0x02222222
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#define CFG_MPP_CONTROL_1 0x11333011
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#define CFG_MPP_CONTROL_2 0x40431111
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#define CFG_MPP_CONTROL_3 0x00000044
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/*# define CFG_SERIAL_PORT_MUX 0x00000102 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */
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# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 1111 1001 0000 1111 1100 0000 0000 0000*/
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/* gpp[31] gpp[30] gpp[29] gpp[28] */
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/* gpp[27] gpp[24]*/
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/* gpp[19:14] */
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/* setup new config_value for MV64360 DDR-RAM !! */
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# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
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#define CFG_DUART_IO CFG_DEV2_SPACE
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#define CFG_DUART_CHAN 1 /* channel to use for console */
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#define CFG_INIT_CHAN1
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#define CFG_INIT_CHAN2
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#define SRAM_BASE CFG_DEV0_SPACE
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#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_EEPRO100 /* ronen - Support for Intel 82557/82559/82559ER chips */
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/* PCI MEMORY MAP section */
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#define CFG_PCI0_MEM_BASE 0x80000000
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#define CFG_PCI0_MEM_SIZE _128M
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#define CFG_PCI1_MEM_BASE 0x88000000
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#define CFG_PCI1_MEM_SIZE _128M
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#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
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#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
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/* PCI I/O MAP section */
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#define CFG_PCI0_IO_BASE 0xfa000000
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#define CFG_PCI0_IO_SIZE _16M
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#define CFG_PCI1_IO_BASE 0xfb000000
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#define CFG_PCI1_IO_SIZE _16M
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#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
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#define CFG_PCI0_IO_SPACE_PCI (CFG_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
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#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
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#define CFG_PCI1_IO_SPACE_PCI (CFG_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
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#if defined (CONFIG_750CX)
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#define CFG_PCI_IDSEL 0x0
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#else
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#define CFG_PCI_IDSEL 0x30
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#endif
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/*----------------------------------------------------------------------
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* Initial BAT mappings
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*/
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/* NOTES:
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* 1) GUARDED and WRITE_THRU not allowed in IBATS
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* 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
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*/
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/* SDRAM */
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#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
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#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CFG_DBAT0U CFG_IBAT0U
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/* init ram */
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#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
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#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
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#define CFG_DBAT1L CFG_IBAT1L
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#define CFG_DBAT1U CFG_IBAT1U
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/* PCI0, PCI1 in one BAT */
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#define CFG_IBAT2L BATL_NO_ACCESS
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#define CFG_IBAT2U CFG_DBAT2U
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#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
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#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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/* GT regs, bootrom, all the devices, PCI I/O */
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#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
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#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
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#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
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#define CFG_DBAT3U CFG_IBAT3U
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/* I2C addresses for the two DIMM SPD chips */
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#define DIMM0_I2C_ADDR 0x56
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#define DIMM1_I2C_ADDR 0x54
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
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#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */
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#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */
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#define CFG_BOOT_FLASH_WIDTH 1 /* 8 bit */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
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#define CFG_FLASH_CFI 1
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
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#define CFG_ENV_SECT_SIZE 0x10000
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#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
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/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* L2CR setup -- make sure this is right for your board!
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* look in include/mpc74xx.h for the defines used here
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*/
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#define CFG_L2
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#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
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#define L2_INIT 0
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#else
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#define L2_INIT 0
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/*
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#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
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L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
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*/
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#endif
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#define L2_ENABLE (L2_INIT | L2CR_L2E)
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CFG_BOARD_ASM_INIT 1
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#endif /* __CONFIG_H */
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