upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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156 lines
3.1 KiB
156 lines
3.1 KiB
/*
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* Copyright (C) 2013, Intel Corporation
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: Intel
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*/
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#include <common.h>
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#include <asm/arch/fsp/azalia.h>
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#include <asm/fsp/fsp_support.h>
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/* ALC262 Verb Table - 10EC0262 */
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static const uint32_t verb_table_data13[] = {
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/* Pin Complex (NID 0x11) */
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0x01171cf0,
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0x01171d11,
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0x01171e11,
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0x01171f41,
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/* Pin Complex (NID 0x12) */
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0x01271cf0,
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0x01271d11,
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0x01271e11,
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0x01271f41,
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/* Pin Complex (NID 0x14) */
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0x01471c10,
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0x01471d40,
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0x01471e01,
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0x01471f01,
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/* Pin Complex (NID 0x15) */
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0x01571cf0,
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0x01571d11,
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0x01571e11,
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0x01571f41,
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/* Pin Complex (NID 0x16) */
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0x01671cf0,
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0x01671d11,
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0x01671e11,
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0x01671f41,
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/* Pin Complex (NID 0x18) */
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0x01871c20,
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0x01871d98,
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0x01871ea1,
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0x01871f01,
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/* Pin Complex (NID 0x19) */
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0x01971c21,
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0x01971d98,
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0x01971ea1,
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0x01971f02,
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/* Pin Complex (NID 0x1A) */
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0x01a71c2f,
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0x01a71d30,
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0x01a71e81,
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0x01a71f01,
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/* Pin Complex */
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0x01b71c1f,
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0x01b71d40,
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0x01b71e21,
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0x01b71f02,
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/* Pin Complex */
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0x01c71cf0,
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0x01c71d11,
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0x01c71e11,
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0x01c71f41,
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/* Pin Complex */
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0x01d71c01,
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0x01d71dc6,
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0x01d71e14,
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0x01d71f40,
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/* Pin Complex */
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0x01e71cf0,
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0x01e71d11,
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0x01e71e11,
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0x01e71f41,
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/* Pin Complex */
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0x01f71cf0,
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0x01f71d11,
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0x01f71e11,
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0x01f71f41,
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};
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/*
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* This needs to be in ROM since if we put it in CAR, FSP init loses it when
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* it drops CAR.
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*
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* TODO(sjg@chromium.org): Move to device tree when FSP allows it
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*
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* VerbTable: (RealTek ALC262)
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* Revision ID = 0xFF, support all steps
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* Codec Verb Table For AZALIA
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* Codec Address: CAd value (0/1/2)
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* Codec Vendor: 0x10EC0262
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*/
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static const struct pch_azalia_verb_table azalia_verb_table[] = {
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{
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{
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0x10ec0262,
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0x0000,
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0xff,
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0x01,
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0x000b,
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0x0002,
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},
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verb_table_data13
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}
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};
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const struct pch_azalia_config azalia_config = {
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.pme_enable = 1,
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.docking_supported = 1,
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.docking_attached = 0,
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.hdmi_codec_enable = 1,
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.azalia_v_ci_enable = 1,
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.rsvdbits = 0,
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.azalia_verb_table_num = 1,
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.azalia_verb_table = azalia_verb_table,
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.reset_wait_timer_us = 300
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};
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void update_fsp_upd(struct upd_region *fsp_upd)
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{
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struct memory_down_data *mem;
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/*
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* Configure everything here to avoid the poor hard-pressed user
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* needing to run Intel's binary configuration tool. It may also allow
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* us to support the 1GB single core variant easily.
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*
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* TODO(sjg@chromium.org): Move to device tree
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*/
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fsp_upd->mrc_init_tseg_size = 8;
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fsp_upd->mrc_init_mmio_size = 0x800;
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fsp_upd->emmc_boot_mode = 0xff;
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fsp_upd->enable_sdio = 1;
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fsp_upd->enable_sdcard = 1;
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fsp_upd->enable_hsuart0 = 1;
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fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
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fsp_upd->enable_i2_c0 = 0;
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fsp_upd->enable_i2_c2 = 0;
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fsp_upd->enable_i2_c3 = 0;
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fsp_upd->enable_i2_c4 = 0;
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fsp_upd->enable_xhci = 0;
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fsp_upd->igd_render_standby = 1;
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mem = &fsp_upd->memory_params;
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mem->enable_memory_down = 1;
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mem->dram_speed = 1;
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mem->dimm_width = 1;
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mem->dimm_density = 2;
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mem->dimm_tcl = 0xb;
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mem->dimm_trpt_rcd = 0xb;
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mem->dimm_twr = 0xc;
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mem->dimm_twtr = 6;
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mem->dimm_trrd = 6;
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mem->dimm_trtp = 6;
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mem->dimm_tfaw = 0x14;
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}
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