upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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591 lines
14 KiB
591 lines
14 KiB
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* The RGMII PHYs are provided by the two on-board PHY connected to
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* dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
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* PHY or by the standard four-port SGMII riser card (VSC).
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/fsl_serdes.h>
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#include <asm/immap_85xx.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <malloc.h>
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#include <fsl_dtsec.h>
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#include <vsc9953.h>
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#include "../common/fman.h"
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#include "../common/qixis.h"
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#include "t1040qds_qixis.h"
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#ifdef CONFIG_FMAN_ENET
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/* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
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* Bank 1 -> Lanes A, B, C, D
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* Bank 2 -> Lanes E, F, G, H
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*/
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/* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here
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* means that the mapping must be determined dynamically, or that the lane
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* maps to something other than a board slot.
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*/
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static u8 lane_to_slot[] = {
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0, 0, 0, 0, 0, 0, 0, 0
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};
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/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
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* housed.
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*/
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static int riser_phy_addr[] = {
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CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
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CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
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CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
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CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
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};
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/* Slot2 does not have EMI connections */
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#define EMI_NONE 0xFFFFFFFF
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#define EMI1_RGMII0 0
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#define EMI1_RGMII1 1
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#define EMI1_SLOT1 2
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#define EMI1_SLOT3 3
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#define EMI1_SLOT4 4
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#define EMI1_SLOT5 5
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#define EMI1_SLOT6 6
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#define EMI1_SLOT7 7
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#define EMI2 8
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static int mdio_mux[NUM_FM_PORTS];
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static const char * const mdio_names[] = {
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"T1040_QDS_MDIO0",
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"T1040_QDS_MDIO1",
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"T1040_QDS_MDIO2",
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"T1040_QDS_MDIO3",
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"T1040_QDS_MDIO4",
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"T1040_QDS_MDIO5",
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"T1040_QDS_MDIO6",
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"T1040_QDS_MDIO7",
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};
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struct t1040_qds_mdio {
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u8 muxval;
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struct mii_dev *realbus;
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};
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static const char *t1040_qds_mdio_name_for_muxval(u8 muxval)
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{
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return mdio_names[muxval];
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}
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struct mii_dev *mii_dev_for_muxval(u8 muxval)
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{
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struct mii_dev *bus;
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const char *name = t1040_qds_mdio_name_for_muxval(muxval);
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if (!name) {
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printf("No bus for muxval %x\n", muxval);
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return NULL;
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}
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bus = miiphy_get_dev_by_name(name);
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if (!bus) {
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printf("No bus by name %s\n", name);
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return NULL;
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}
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return bus;
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}
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static void t1040_qds_mux_mdio(u8 muxval)
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{
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u8 brdcfg4;
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if (muxval <= 7) {
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brdcfg4 = QIXIS_READ(brdcfg[4]);
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brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
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brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
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QIXIS_WRITE(brdcfg[4], brdcfg4);
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}
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}
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static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad,
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int regnum)
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{
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struct t1040_qds_mdio *priv = bus->priv;
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t1040_qds_mux_mdio(priv->muxval);
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return priv->realbus->read(priv->realbus, addr, devad, regnum);
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}
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static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
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int regnum, u16 value)
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{
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struct t1040_qds_mdio *priv = bus->priv;
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t1040_qds_mux_mdio(priv->muxval);
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return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
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}
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static int t1040_qds_mdio_reset(struct mii_dev *bus)
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{
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struct t1040_qds_mdio *priv = bus->priv;
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return priv->realbus->reset(priv->realbus);
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}
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static int t1040_qds_mdio_init(char *realbusname, u8 muxval)
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{
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struct t1040_qds_mdio *pmdio;
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate t1040_qds MDIO bus\n");
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return -1;
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}
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pmdio = malloc(sizeof(*pmdio));
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if (!pmdio) {
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printf("Failed to allocate t1040_qds private data\n");
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free(bus);
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return -1;
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}
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bus->read = t1040_qds_mdio_read;
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bus->write = t1040_qds_mdio_write;
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bus->reset = t1040_qds_mdio_reset;
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strcpy(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
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pmdio->realbus = miiphy_get_dev_by_name(realbusname);
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if (!pmdio->realbus) {
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printf("No bus with name %s\n", realbusname);
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free(bus);
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free(pmdio);
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return -1;
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}
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pmdio->muxval = muxval;
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bus->priv = pmdio;
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return mdio_register(bus);
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}
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/*
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* Initialize the lane_to_slot[] array.
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*
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* On the T1040QDS board the mapping is controlled by ?? register.
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*/
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static void initialize_lane_to_slot(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL)
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>> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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QIXIS_WRITE(cms[0], 0x07);
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switch (serdes1_prtcl) {
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case 0x60:
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case 0x66:
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case 0x67:
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case 0x69:
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lane_to_slot[1] = 7;
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lane_to_slot[2] = 6;
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lane_to_slot[3] = 5;
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break;
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case 0x86:
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lane_to_slot[1] = 7;
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lane_to_slot[2] = 7;
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lane_to_slot[3] = 7;
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break;
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case 0x87:
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lane_to_slot[1] = 7;
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lane_to_slot[2] = 7;
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lane_to_slot[3] = 7;
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lane_to_slot[7] = 7;
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break;
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case 0x89:
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lane_to_slot[1] = 7;
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lane_to_slot[2] = 7;
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lane_to_slot[3] = 7;
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lane_to_slot[6] = 7;
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lane_to_slot[7] = 7;
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break;
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case 0x8d:
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lane_to_slot[1] = 7;
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lane_to_slot[2] = 7;
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lane_to_slot[3] = 7;
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lane_to_slot[5] = 3;
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lane_to_slot[6] = 3;
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lane_to_slot[7] = 3;
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break;
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case 0x8F:
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case 0x85:
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lane_to_slot[1] = 7;
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lane_to_slot[2] = 6;
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lane_to_slot[3] = 5;
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lane_to_slot[6] = 3;
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lane_to_slot[7] = 3;
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break;
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case 0xA5:
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lane_to_slot[1] = 7;
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lane_to_slot[6] = 3;
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lane_to_slot[7] = 3;
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break;
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case 0xA7:
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lane_to_slot[1] = 7;
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lane_to_slot[2] = 6;
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lane_to_slot[3] = 5;
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lane_to_slot[7] = 7;
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break;
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case 0xAA:
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lane_to_slot[1] = 7;
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lane_to_slot[6] = 7;
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lane_to_slot[7] = 7;
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break;
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case 0x40:
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lane_to_slot[2] = 7;
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lane_to_slot[3] = 7;
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break;
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default:
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printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n",
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serdes1_prtcl);
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break;
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}
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}
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/*
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* Given the following ...
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*
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* 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
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* compatible string and 'addr' physical address)
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*
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* 2) An Fman port
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*
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* ... update the phy-handle property of the Ethernet node to point to the
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* right PHY. This assumes that we already know the PHY for each port.
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*
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* The offset of the Fman Ethernet node is also passed in for convenience, but
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* it is not used, and we recalculate the offset anyway.
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*
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* Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
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* Inside the Fman, "ports" are things that connect to MACs. We only call them
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* ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
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* and ports are the same thing.
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*
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*/
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void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
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enum fm_port port, int offset)
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{
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phy_interface_t intf = fm_info_get_enet_if(port);
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char phy[16];
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/* The RGMII PHY is identified by the MAC connected to it */
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if (intf == PHY_INTERFACE_MODE_RGMII) {
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sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
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fdt_set_phy_handle(fdt, compat, addr, phy);
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}
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/* The SGMII PHY is identified by the MAC connected to it */
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if (intf == PHY_INTERFACE_MODE_SGMII) {
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int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
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+ port);
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u8 slot;
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if (lane < 0)
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return;
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slot = lane_to_slot[lane];
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if (slot) {
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/* Slot housing a SGMII riser card */
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sprintf(phy, "phy_s%x_%02x", slot,
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(fm_info_get_phy_address(port - FM1_DTSEC1)-
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CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
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fdt_set_phy_handle(fdt, compat, addr, phy);
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}
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}
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}
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void fdt_fixup_board_enet(void *fdt)
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{
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int i, lane, idx;
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for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
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idx = i - FM1_DTSEC1;
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_SGMII:
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lane = serdes_get_first_lane(FSL_SRDS_1,
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SGMII_FM1_DTSEC1 + idx);
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if (lane < 0)
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break;
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switch (mdio_mux[i]) {
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case EMI1_SLOT3:
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fdt_status_okay_by_alias(fdt, "emi1_slot3");
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break;
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case EMI1_SLOT5:
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fdt_status_okay_by_alias(fdt, "emi1_slot5");
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break;
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case EMI1_SLOT6:
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fdt_status_okay_by_alias(fdt, "emi1_slot6");
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break;
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case EMI1_SLOT7:
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fdt_status_okay_by_alias(fdt, "emi1_slot7");
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break;
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}
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break;
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case PHY_INTERFACE_MODE_RGMII:
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if (i == FM1_DTSEC4)
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fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
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if (i == FM1_DTSEC5)
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fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
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break;
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default:
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break;
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}
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}
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}
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#endif /* #ifdef CONFIG_FMAN_ENET */
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static void set_brdcfg9_for_gtx_clk(void)
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{
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u8 brdcfg9;
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brdcfg9 = QIXIS_READ(brdcfg[9]);
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/* Initializing EPHY2 clock to RGMII mode */
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brdcfg9 &= ~(BRDCFG9_EPHY2_MASK);
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brdcfg9 |= (BRDCFG9_EPHY2_VAL);
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QIXIS_WRITE(brdcfg[9], brdcfg9);
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}
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void t1040_handle_phy_interface_sgmii(int i)
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{
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int lane, idx, slot;
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idx = i - FM1_DTSEC1;
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lane = serdes_get_first_lane(FSL_SRDS_1,
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SGMII_FM1_DTSEC1 + idx);
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if (lane < 0)
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return;
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slot = lane_to_slot[lane];
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switch (slot) {
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case 1:
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mdio_mux[i] = EMI1_SLOT1;
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fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
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break;
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case 3:
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if (FM1_DTSEC4 == i)
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fm_info_set_phy_address(i, riser_phy_addr[0]);
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if (FM1_DTSEC5 == i)
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fm_info_set_phy_address(i, riser_phy_addr[1]);
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mdio_mux[i] = EMI1_SLOT3;
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fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
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break;
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case 4:
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mdio_mux[i] = EMI1_SLOT4;
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fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
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break;
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case 5:
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/* Slot housing a SGMII riser card? */
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fm_info_set_phy_address(i, riser_phy_addr[0]);
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mdio_mux[i] = EMI1_SLOT5;
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fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
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break;
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case 6:
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/* Slot housing a SGMII riser card? */
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fm_info_set_phy_address(i, riser_phy_addr[0]);
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mdio_mux[i] = EMI1_SLOT6;
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fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
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break;
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case 7:
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if (FM1_DTSEC1 == i)
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fm_info_set_phy_address(i, riser_phy_addr[0]);
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if (FM1_DTSEC2 == i)
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fm_info_set_phy_address(i, riser_phy_addr[1]);
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if (FM1_DTSEC3 == i)
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fm_info_set_phy_address(i, riser_phy_addr[2]);
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if (FM1_DTSEC5 == i)
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fm_info_set_phy_address(i, riser_phy_addr[3]);
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mdio_mux[i] = EMI1_SLOT7;
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fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
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break;
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default:
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break;
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}
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fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
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}
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void t1040_handle_phy_interface_rgmii(int i)
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{
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fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
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CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
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CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
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mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 :
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EMI1_RGMII0;
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fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
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}
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_FMAN_ENET
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struct memac_mdio_info memac_mdio_info;
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unsigned int i;
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#ifdef CONFIG_VSC9953
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int lane;
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int phy_addr;
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phy_interface_t phy_int;
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struct mii_dev *bus;
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#endif
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printf("Initializing Fman\n");
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set_brdcfg9_for_gtx_clk();
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initialize_lane_to_slot();
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/* Initialize the mdio_mux array so we can recognize empty elements */
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for (i = 0; i < NUM_FM_PORTS; i++)
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mdio_mux[i] = EMI_NONE;
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memac_mdio_info.regs =
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(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
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memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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/* Register the real 1G MDIO bus */
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fm_memac_mdio_init(bis, &memac_mdio_info);
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/* Register the muxing front-ends to the MDIO buses */
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t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0);
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t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
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t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
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t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
|
|
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
|
|
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
|
|
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
|
|
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
|
|
|
|
/*
|
|
* Program on board RGMII PHY addresses. If the SGMII Riser
|
|
* card used, we'll override the PHY address later. For any DTSEC that
|
|
* is RGMII, we'll also override its PHY address later. We assume that
|
|
* DTSEC4 and DTSEC5 are used for RGMII.
|
|
*/
|
|
fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
|
|
fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
|
|
|
|
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
|
|
switch (fm_info_get_enet_if(i)) {
|
|
case PHY_INTERFACE_MODE_QSGMII:
|
|
fm_info_set_mdio(i, NULL);
|
|
break;
|
|
case PHY_INTERFACE_MODE_SGMII:
|
|
t1040_handle_phy_interface_sgmii(i);
|
|
break;
|
|
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
|
|
t1040_handle_phy_interface_rgmii(i);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_VSC9953
|
|
for (i = 0; i < VSC9953_MAX_PORTS; i++) {
|
|
lane = -1;
|
|
phy_addr = 0;
|
|
phy_int = PHY_INTERFACE_MODE_NONE;
|
|
switch (i) {
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);
|
|
/* PHYs connected over QSGMII */
|
|
if (lane >= 0) {
|
|
phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR +
|
|
i;
|
|
phy_int = PHY_INTERFACE_MODE_QSGMII;
|
|
break;
|
|
}
|
|
lane = serdes_get_first_lane(FSL_SRDS_1,
|
|
SGMII_SW1_MAC1 + i);
|
|
|
|
if (lane < 0)
|
|
break;
|
|
|
|
/* PHYs connected over QSGMII */
|
|
if (i != 3 || lane_to_slot[lane] == 7)
|
|
phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
|
|
+ i;
|
|
else
|
|
phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR;
|
|
phy_int = PHY_INTERFACE_MODE_SGMII;
|
|
break;
|
|
case 4:
|
|
case 5:
|
|
case 6:
|
|
case 7:
|
|
lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B);
|
|
/* PHYs connected over QSGMII */
|
|
if (lane >= 0) {
|
|
phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR +
|
|
i - 4;
|
|
phy_int = PHY_INTERFACE_MODE_QSGMII;
|
|
break;
|
|
}
|
|
lane = serdes_get_first_lane(FSL_SRDS_1,
|
|
SGMII_SW1_MAC1 + i);
|
|
/* PHYs connected over SGMII */
|
|
if (lane >= 0) {
|
|
phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
|
|
+ i - 3;
|
|
phy_int = PHY_INTERFACE_MODE_SGMII;
|
|
}
|
|
break;
|
|
case 8:
|
|
if (serdes_get_first_lane(FSL_SRDS_1,
|
|
SGMII_FM1_DTSEC1) < 0)
|
|
/* FM1@DTSEC1 is connected to SW1@PORT8 */
|
|
vsc9953_port_enable(i);
|
|
break;
|
|
case 9:
|
|
if (serdes_get_first_lane(FSL_SRDS_1,
|
|
SGMII_FM1_DTSEC2) < 0) {
|
|
/* Enable L2 On MAC2 using SCFG */
|
|
struct ccsr_scfg *scfg = (struct ccsr_scfg *)
|
|
CONFIG_SYS_MPC85xx_SCFG;
|
|
|
|
out_be32(&scfg->esgmiiselcr,
|
|
in_be32(&scfg->esgmiiselcr) |
|
|
(0x80000000));
|
|
vsc9953_port_enable(i);
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (lane >= 0) {
|
|
bus = mii_dev_for_muxval(lane_to_slot[lane]);
|
|
vsc9953_port_info_set_mdio(i, bus);
|
|
vsc9953_port_enable(i);
|
|
}
|
|
vsc9953_port_info_set_phy_address(i, phy_addr);
|
|
vsc9953_port_info_set_phy_int(i, phy_int);
|
|
}
|
|
|
|
#endif
|
|
cpu_eth_init(bis);
|
|
#endif
|
|
|
|
return pci_eth_init(bis);
|
|
}
|
|
|