upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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113 lines
2.4 KiB
113 lines
2.4 KiB
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Clock drivers for Qualcomm APQ8016
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*
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* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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*
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* Based on Little Kernel driver, simplified
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include "clock-snapdragon.h"
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/* GPLL0 clock control registers */
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#define GPLL0_STATUS_ACTIVE BIT(17)
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static const struct bcr_regs sdc_regs[] = {
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{
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.cfg_rcgr = SDCC_CFG_RCGR(1),
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.cmd_rcgr = SDCC_CMD_RCGR(1),
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.M = SDCC_M(1),
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.N = SDCC_N(1),
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.D = SDCC_D(1),
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},
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{
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.cfg_rcgr = SDCC_CFG_RCGR(2),
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.cmd_rcgr = SDCC_CMD_RCGR(2),
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.M = SDCC_M(2),
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.N = SDCC_N(2),
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.D = SDCC_D(2),
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}
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};
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static struct pll_vote_clk gpll0_vote_clk = {
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.status = GPLL0_STATUS,
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.status_bit = GPLL0_STATUS_ACTIVE,
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.ena_vote = APCS_GPLL_ENA_VOTE,
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.vote_bit = BIT(0),
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};
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static struct vote_clk gcc_blsp1_ahb_clk = {
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.cbcr_reg = BLSP1_AHB_CBCR,
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.ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
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.vote_bit = BIT(10),
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};
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/* SDHCI */
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static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
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{
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int div = 8; /* 100MHz default */
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if (rate == 200000000)
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div = 4;
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clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot));
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/* 800Mhz/div, gpll0 */
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clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0,
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CFG_CLK_SRC_GPLL0);
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clk_enable_gpll0(priv->base, &gpll0_vote_clk);
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clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
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return rate;
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}
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static const struct bcr_regs uart2_regs = {
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.cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
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.cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
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.M = BLSP1_UART2_APPS_M,
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.N = BLSP1_UART2_APPS_N,
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.D = BLSP1_UART2_APPS_D,
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};
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/* UART: 115200 */
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static int clk_init_uart(struct msm_clk_priv *priv)
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{
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/* Enable AHB clock */
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clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
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/* 7372800 uart block clock @ GPLL0 */
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clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625,
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CFG_CLK_SRC_GPLL0);
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/* Vote for gpll0 clock */
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clk_enable_gpll0(priv->base, &gpll0_vote_clk);
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/* Enable core clk */
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clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
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return 0;
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}
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ulong msm_set_rate(struct clk *clk, ulong rate)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case 0: /* SDC1 */
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return clk_init_sdc(priv, 0, rate);
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break;
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case 1: /* SDC2 */
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return clk_init_sdc(priv, 1, rate);
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break;
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case 4: /* UART2 */
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return clk_init_uart(priv);
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break;
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default:
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return 0;
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}
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}
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